16 16点阵显示汉字原理及显示程序 #include "config.h" #define DOTLED_LINE_PORT PORTB #define DOTLED_LINE_DDR DDRB #define DOTLED_LINE_PIN PINB #define DOTLED_LINE_SCKT PB1 #define DOTLED_LINE_SCKH PB5 #define DOTLED_LINE_SDA PB3 #define DOTLED_ROW_PORT PORTC #define DOTLED_ROW_DDR DDRC #define DOTLED_ROW_PIN PINC #define DOTLED_ROW_A0 PC0 #define DOTLED_ROW_A1 PC1 #define DOTLED_ROW_A2 PC2 #define DOTLED_ROW_A3 PC3 #define DOTLED_ROW_E PC4 uint8 font[] = { /*-- 调入了一幅图像：这是您新建的图像 --*/ /*-- 宽度x高度=16x16 --*/ 0x00,0x00,0x00,0x00,0x08,0x38,0x18,0x44,0x08,0x44,0x08,0x04,0x08,0x08,0x08,0x10, 0x08,0x20,0x08,0x40,0x08,0x40,0x08,0x40,0x3E,0x7C,0x00,0x00,0x00,0x00,0x00,0x00 }; static void TransmitByte(uint8 byte); static void SelectRow(uint8 row); static void FlipLatchLine(void); static void TransmitByte(uint8 byte) { uint8 i; for(i = 0 ; i < 8 ; i ++) { if(byte & (1 << i)) { DOTLED_LINE_PORT |= _BV(DOTLED_LINE_SDA); } else { DOTLED_LINE_PORT &= ~_BV(DOTLED_LINE_SDA); } //__delay_cycles(100); DOTLED_LINE_PORT |= _BV(DOTLED_LINE_SCKH); //__delay_cycles(100); DOTLED_LINE_PORT &= ~_BV(DOTLED_LINE_SCKH); //__delay_cycles(100); } } static void SelectRow(uint8 row) { //row -= 1; row |= DOTLED_ROW_PIN & 0xe0; DOTLED_ROW_PORT = row; } static void FlipLatchLine(void) { DOTLED_LINE_PORT |= _BV(DOTLED_LINE_SCKT); DOTLED_LINE_PORT &= ~_BV(DOTLED_LINE_SCKT); } void InitDotLedPort(void) { DOTLED_LINE_PORT &= ~(_BV(DOTLED_LINE_SCKT) | _BV(DOTLED_LINE_SCKH)); DOTLED_LINE_PORT |= _BV(DOTLED_LINE_SDA); DOTLED_LINE_DDR |= _BV(DOTLED_LINE_SCKT) | _BV(DOTLED_LINE_SCKH) | _BV(DOTLED_LINE_SDA); DOTLED_ROW_PORT |= 0x1f; DOTLED_ROW_PORT &= 0xf0; DOTLED_ROW_DDR |= 0x1f; } void EnableRow(boolean IsEnable) { if(IsEnable) { DOTLED_ROW_PORT &= ~_BV(DOTLED_ROW_E); } else { DOTLED_ROW_PORT |= _BV(DOTLED_ROW_E); } } void PrintDotLed(uint8 * buffer) { uint8 i , tmp; for(i = 0 ; i < 16 ; i ++) { tmp = *buffer ++; TransmitByte(~tmp); tmp = *buffer ++; TransmitByte(~tmp); SelectRow(i); FlipLatchLine(); } } void main(void) { InitDotLedPort(); EnableRow(TRUE); while(1) { PrintDotLed(font); __delay_cycles(5000); } } //---------------------------------------------------- config.h文件 #ifndef _CONFIG_H #define _CONFIG_H //#define GCCAVR #define CPU_CYCLES 7372800L #ifndef GCCAVR #define _BV(bit) (1 << (bit)) #endif #define MSB 0x80 #define LSB 0x01 #define FALSE 0 #define TRUE 1 typedef unsigned char uint8; typedef unsigned int uint16; typedef unsigned long uint32; typedef unsigned char boolean; #include <ioavr.h> #include <inavr.h> #include "dotled.h" #endif //-----
上传时间： 2013-11-18
上传用户：mnacyf
51单片机驱动步进电机(含电路图和源程序代码） 源程序:stepper.c stepper.hex /* * STEPPER.C * sweeping stepper's rotor cw and cww 400 steps * Copyright (c) 1999 by W.Sirichote */ ＃i nclude c:\mc5151io.h /* include i/o header file */ ＃i nclude c:\mc5151reg.h register unsigned char j,flag1,temp; register unsigned int cw_n,ccw_n; unsigned char step[8]={0x80,0xc0,0x40,0x60,0x20,0x30,0x10,0x90} #define n 400 /* flag1 mask byte 0x01 run cw() 0x02 run ccw() */
上传时间： 2013-11-09
上传用户：钓鳌牧马
C语言编程基础：1. 十六进制表示字节0x5a：二进制为01011010B；0x6E为01101110。 2. 如果将一个16位二进数赋给一个8位的字节变量，则自动截断为低8位，而丢掉高8位。 3. ++var表示对变量var先增一；var—表示对变量后减一。 4. x |= 0x0f;表示为 x = x | 0x0f; 5. TMOD = ( TMOD & 0xf0 ) | 0x05;表示给变量TMOD的低四位赋值0x5，而不改变TMOD的高四位。 6. While( 1 ); 表示无限执行该语句，即死循环。语句后的分号表示空循环体，也就是{;} 在某引脚输出高电平的编程方法：（比如P1.3（PIN4）引脚）1. #include <AT89x52.h> //该头文档中有单片机内部资源的符号化定义，其中包含P1.3 2. void main( void ) //void 表示没有输入参数，也没有函数返值，这入单片机运行的复位入口 3. { 4. P1_3 = 1; //给P1_3赋值1，引脚P1.3就能输出高电平VCC 5. While( 1 ); //死循环，相当 LOOP: goto LOOP; 6. } 注意：P0的每个引脚要输出高电平时，必须外接上拉电阻（如4K7）至VCC电源。在某引脚输出低电平的编程方法：（比如P2.7引脚）代码1. #include <AT89x52.h> //该头文档中有单片机内部资源的符号化定义，其中包含P2.7 2. void main( void ) //void 表示没有输入参数，也没有函数返值，这入单片机运行的复位入口 3. { 4. P2_7 = 0; //给P2_7赋值0，引脚P2.7就能输出低电平GND 5. While( 1 ); //死循环，相当 LOOP: goto LOOP; 6. } 在某引脚输出方波编程方法：（比如P3.1引脚）代码1. #include <AT89x52.h> //该头文档中有单片机内部资源的符号化定义，其中包含P3.1 2. void main( void ) //void 表示没有输入参数，也没有函数返值，这入单片机运行的复位入口 3. { 4. While( 1 ) //非零表示真，如果为真则执行下面循环体的语句 5. { 6. P3_1 = 1; //给P3_1赋值1，引脚P3.1就能输出高电平VCC 7. P3_1 = 0; //给P3_1赋值0，引脚P3.1就能输出低电平GND 8. } //由于一直为真，所以不断输出高、低、高、低……，从而形成方波 9. } 将某引脚的输入电平取反后，从另一个引脚输出：（ 比如 P0.4 = NOT( P1.1) ）
上传时间： 2013-11-02
上传用户：zengduo
/* 4位8段数码管分别动态显示“1234”， */ #include "7LEDShow.h" void main() { DIGPORT = 0; // 关闭显示 TMOD = 0x01; // T0工作方式1 /* 2ms 定时设置 */ time0_tmp = 65536-time0*fosc/12; TH0 = (time0_tmp/256); TL0 = (time0_tmp%256); TR0 = 1; ET0 = 1; EA = 1; digbit = 0x01; // 从第一位数码管开始
上传时间： 2013-12-12
上传用户：kachleen
EEPROM为ATMEL公司的AT24C01A。单片机为ATMEL公司的AT89C51。2. 软件说明 C语言为Franklin C V3.2。将源程序另存为testi2c.c，用命令C51 testi2c.cL51 TESTI2C.OBJOHS51 TESTI2C编译，连接，得到TESTI2C.HEX文件，即可由编程器读入并进行写片，实验。3．源程序#include <reg51.h>#include <intrins.h> #define uchar unsigned char#define uint unsigned int#define AddWr 0xa0 /*器件地址选择及写标志*/#define AddRd 0xa1 /*器件地址选择及读标志*/#define Hidden 0x0e /*显示器的消隐码*/
上传时间： 2013-10-09
上传用户：hjshhyy
include "macrodefine.h"#include "lpc2294.h" //ADS1210初始化子程序void AD_Init(void){ Delayus(2); SPI1_Communation(0x64); SPI1_Communation(0x72); //单极性，SDOUT独立，先MSB，REF使用内部 SPI1_Communation(0x20); //自校准模式，增益1，通道0 SPI1_Communation(0x87); //TURBO=16， SPI1_Communation(0xa0); //数据更新率100}//读取ADS1210转换结果子程序uint32 Read_AD_Data(void){ uint8 i=0; uint8 Data_Temp[3]; uint32 Result_HEX=0; Delayus(1); SPI1_Communation(0xc0); for(i=0;i<3;i++) { Data_Temp[i] =SPI1_Communation(0xff); }
上传时间： 2013-10-10
上传用户：suicone
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 图Figure 1. Local Safety System
上传时间： 2013-11-05
上传用户：维子哥哥
Abstract: There are many things to consider when designing a power supply for a field-programmablegate array (FPGA). These include (but are not limited to) the high number of voltage rails, and thediffering requirements for both sequencing/tracking and the voltage ripple limits. This application noteexplains these and other power-supply considerations that an engineer must think through whendesigning a power supply for an FPGA.
上传时间： 2013-11-10
上传用户：iswlkje
UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
上传时间： 2013-11-07
上传用户：jasson5678
