阐述了轨道交通列车定位技术。介绍了在轨道交通系统中列车定位技术的功能，国内外轨道交通中主要采用的列车定位方法，重点论述了几种主要定位技术，并从定位精度、闭塞制式、维护投资成本、抗干扰等方面进行分析比较。提出目前轨道交通定位技术应综合运用，取长补短，多种方法相互融合，才能满足轨道交通中对安全可靠性的要求。 Abstract: Rail train positioning technology is described. The paper introduces the funetions of the train positioning technology in the rail transit system， the main methods of train positioning do mestic and international rail， and focuses on several key methods， analyzes and compares from the positioning accuracy， block system, maintenance and investment cost， interference and SO on， suggested that the current rail positioning technology should be integrated use of positioning method of meriging， learn from each other， to meet the reliability requirements of rail safety.
上传时间： 2013-11-25
上传用户：franktu
针对UHF读写器设计中，在符合EPC Gen2标准的情况下，对标签返回的高速数据进行正确解码以达到正确读取标签的要求，提出了一种新的在ARM平台下采用边沿捕获统计定时器数判断数据的方法，并对FM0编码进行解码。与传统的使用定时器定时采样高低电平的FM0解码方法相比，该解码方法可以减少定时器定时误差累积的影响；可以将捕获定时器数中断与数据判断解码相对分隔开，使得中断对解码影响很小，实现捕获与解码的同步。通过实验表明，这种方法提高了解码的效率，在160 Kb/s的接收速度下，读取一张标签的时间约为30次/s。 Abstract: Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator， the article introduced a new technology for FM0 decoding which counted the timer counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level， the method could reduce the accumulation of timing error and could relatively separate capture timer interrupt and the data judgment for decoding， SO that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding， at 160 Kb/s receiving speed， the time of the interrogator to read a tag is about 30 times/s.
上传时间： 2013-11-10
上传用户：liufei
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a SOftware failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. SO the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上传时间： 2013-11-11
上传用户：gundamwzc
C++在几乎所有的计算环境中都非常普及，而且可以用于几乎所有的应用程序。C++从C中继承了过程化编程的高效性，并集成了面向对象编程的功能。C++在其标准库中提供了大量的功能。有许多商业C++库支持数量众多的操作系统环境和专业应用程序。但因为它的内容太多了，所以掌握C++并不十分容易。本书详述了C++语言的各个方面，包括数据类型、程序控制、函数、指针、调试、类、重载、继承、多态性、模板、异常和输入输出等内容。每一章都以前述内容为基础，每个关键点都用具体的示例进行详细的讲解。本书基本不需要读者具备任何C++知识，书中包含了理解C++的所有必要知识，读者可以从头开始编写自己的C++程序。本书也适合于具备另一种语言编程经验但希望全面掌握C++语言的读者。 I created all the files under MicroSOft Windows SO lines are terminated by CR/LF. In addition to this "ReadMe" file you will find three zip archives in the primary archive, SO you need to unzip each of these to get at the code. 为PDG格式,这有pdg阅读器下载|pdg文件阅读器下载
标签： 源代码
上传时间： 2013-11-18
上传用户：gaoqinwu
There has long been a need for portable ultraSOundsystems that have good reSOlution at affordable costpoints. Portable systems enable healthcare providersto use ultraSOund in remote locations such asdisaster zones, developing regions, and battlefields,where it was not previously practical to do SO.
上传时间： 2015-01-01
上传用户：hfnishi
SOPC嵌入式系统实验教程（一）【作者：周立功；出版社：北京航空航天大学出版社】(因网上资料有限，所以本资料为周立功 SOPC嵌入式系统实验教程（一）部分章节及实验代码，真心想学的可以买一本书看看。) 该书是与《SOPC嵌入式系统基础教程》相配套的实验教材。设计开发了 45个实验，包括SOPC硬件系统的基础实验，基于Nios II外设的基础编程实验，基于实验箱外设的Nios II高级编程实验，在Nios II系统中进行基于μ C/OS-II操作系统的应用程序开发实验和SOPC硬件系统的高级实验。各种实验的安排由浅人深，由硬件到软件，相对完整，使读者很容易学习和掌握SO PC嵌入式系统的开发应用。
上传时间： 2013-11-01
上传用户：superman111
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocesSOr application. This reference system alSO uses a DCM that isconfigured SO that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a SOftwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocesSOr.
上传时间： 2014-11-26
上传用户：erkuizhang
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do SO within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another SOlution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this SOlution increases the required power and clock reSOurce usage.
上传时间： 2013-11-24
上传用户：18707733937
本文简单讨论并总结了VHDL、Verilog，System verilog 这三中语言的各自特点和区别As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, SO too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
标签： Verilog verilog System VHDL
上传时间： 2014-03-03
上传用户：zhtzht
Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these SO that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.
上传时间： 2013-10-22
上传用户：lmq0059
