This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently suppor...
探索sm-BUS技术的精髓,掌握现代电子设计的关键。sm-BUS(系统管理总线)以其高效的数据传输能力和低功耗特性,在计算机硬件监控、电源管理和传感器网络等领域发挥着重要作用。本页面汇集了540个精选资源,包括教程、案例分析和技术文档,旨在帮助工程师深入了解sm-BUS协议的工作原理及其在实际项目中...
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently suppor...
Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.
SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口,方便与其他IP连接使用。
load flow algorithm, with entering bus data and line data it solves the load flow with newton method.
This program is a series of 51 single-chip microcomputer simulation IIC bus, the memory of the 24 operations