本模拟I2C软件包包含了I2C操作的底层子程序，使用前要定义 好SCL和SDA。在标准8051模式(12 Clock)下,对主频要求是不高于12MHz(即1个 机器周期1us) 若Fosc>12MHz则要增加相应的NOP指令数。(总线时序符合I2C标 准模式,100Kbit/S)。
上传时间： 2013-12-08
上传用户：ruixue198909
The DHRY program performs the dhrystone benchmarks on the 8051. Dhrystone is a general-performance benchmark test originally developed by Reinhold Weicker in 1984. This benchmark is used to measure and compare the performance of different computers or, in this case, the efficiency of the code generated for the same computer by different compilers. The test reports general performance in dhrystones per second. Like most benchmark programs, dhrystone consists of standard code and concentrates on string handling. It uses no floating-point operations. It is heavily influenced by hardware and software design, compiler and linker options, code optimizing, cache memory, wait states, and integer data types. The DHRY program is available in different targets: Simulator: Large Model: DHRY example in LARGE model for Simulation Philips 80C51MX: DHRY example in LARGE model for the Philips 80C51MC
标签： general-performanc benchmarks Dhrystone dhrystone
上传时间： 2016-11-30
上传用户：hphh
MATLAB Code for Optimal Quincunx Filter Bank Design Yi Chen July 17, 2006 This file introduces the MATLAB code that implements the two algorithms (i.e., Algorithms 1 and 2 in [1], or Algorithms 4.1 and 4.2 in [2]) used for the construction of quincunx filter banks with perfect reconstruction, linear phase, high coding gain, certain vanishing moments properties, and good frequency selectivity. The code can be used to design quincunx filter banks with two, three, or four lifting steps. The SeDuMi Matlab toolbox [3] is used to solve the second-order cone programming subproblems in the two algorithms, and must be installed in order for this code to work.
标签： introduces Quincunx Optimal MATLAB
上传时间： 2014-01-15
上传用户：cc1
本文挡主要探讨一些web代码安全里比较隐秘，容易被程序员忽视的问题． 主要内容： 二次攻击[Second attack] 类型1：通过文件系统函数漏洞转换 类型2：通过SQL注射漏洞转换 类型3：通过正则表达式中转变量 类型4：通过编码/解码中转变量 数组变量的魅力 Code与系统 Code与http协议 漏洞挖掘
上传时间： 2016-12-13
上传用户：佳期如梦
DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上传时间： 2014-11-01
上传用户：l254587896
利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER， 设计一个20bit的up_only COUNTER, 要求该COUNTER在FE0FA和FFFFF之间自动循环计数； 分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、 EPF10K70RC240-4几种芯片中的最大工作频率； 请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来 （仅EPF10K70RC240-4芯片,最大允许Clock频率下）。
标签： MegaWizard QuartusII Manager COMPARE
上传时间： 2016-12-26
上传用户：王者A
Batch version of the back-propagation algorithm. ％ Given a set of corresponding input-output pairs and an initial network ％ [W1,W2,critvec,iter]=batbp(NetDef,W1,W2,PHI,Y,trparms) trains the ％ network with backpropagation. ％ ％ The activation functions must be either linear or tanh. The network ％ architecture is defined by the matrix NetDef consisting of two ％ rows. The first row specifies the hidden layer while the second ％ specifies the output layer. ％
标签： back-propagation corresponding input-output algorithm
上传时间： 2016-12-27
上传用户：exxxds
％ Train a two layer neural network with the Levenberg-Marquardt ％ method. ％ ％ If desired, it is possible to use regularization by ％ weight decay. Also pruned (ie. not fully connected) networks can ％ be trained. ％ ％ Given a set of corresponding input-output pairs and an initial ％ network, ％ [W1,W2,critvec,iteration,lambda]=marq(NetDef,W1,W2,PHI,Y,trparms) ％ trains the network with the Levenberg-Marquardt method. ％ ％ The activation functions can be either linear or tanh. The ％ network architecture is defined by the matrix NetDef which ％ has two rows. The first row specifies the hidden layer and the ％ second row specifies the output layer.
标签： Levenberg-Marquardt desired network neural
上传时间： 2016-12-27
上传用户：jcljkh
Train a two layer neural network with a recursive prediction error ％ algorithm ("recursive Gauss-Newton"). Also pruned (i.e., not fully ％ connected) networks can be trained. ％ ％ The activation functions can either be linear or tanh. The network ％ architecture is defined by the matrix NetDef , which has of two ％ rows. The first row specifies the hidden layer while the second ％ specifies the output layer.
标签： recursive prediction algorithm Gauss-Ne
上传时间： 2016-12-27
上传用户：ljt101007
595——8位数码管循环移位显示.doc │ 利用74HC595实现多位LED显示的新方法.doc │ 用74HC595芯片驱动LED的电路设计.pdf │ 文件目录表绘制.cmd │ 文件夹目录.txt │ 文件名目录.txt │ ├─点阵设计 │ 74HC595PW.pdf │ 正文点阵设计.doc │ ├─Use595_4(Alexi) │ Use595_2.c │ Use595_4.hex │ Use595_4(Alexi).PWI │ Use595_4(Alexi).DSN │ ├─电子钟（595） │ Eclock_2.hex │ Eclock_2.c │ Eclock_2.Opt │ Eclock_2.Uv2 │ Eclock_2_1.hex │ E-Clock.DSN │ E-Clock.PWI │ └─资料介绍 595.jpg 74HC595真值表.png 74hc595.doc ★595引脚介绍★.doc 74HC595PW.pdf
上传时间： 2014-01-07
上传用户：aa17807091
