基于频率插值的4.0kbps 语音编码器的性能和设计（英文）
The 4.0 kbit/s speech codec described in this paper is based on a Frequency Domain Interpolative (FD...
Phase-lo技术资料
📦 资源总数：235
💻 源代码：18030
🔌 电路图：3
📚 Phase-lo全部资料 (235个)
三相整流器LCL滤波器设计
Design and Control of an LCL-filter-based three-phase active rectifier 早期的文章...
xc8配置字
//CONFIG 1 #pragma config FCMEN=OFF,IESO=OFF,CLKOUTEN=OFF,BOREN=NSLEEP,CPD=OFF #pragma...
GSM 03.40
Digital cellular telecommunications system (Phase 2+); Technical realization of the Short Message Se...
GSM 03.48
Digital cellular telecommunications system (Phase 2+); Security mechanisms for SIM application toolk...
AD810
PRODUCT DESCRIPTION The AD810 is a composite and HDTV compatible, current feedback, video op...
AD8001AR
transimpedance linearization circuitry. This allows it to drive video loads with excellent diff...
Digital Processing Optical Transmission
Optical communication technology has been extensively developed over the last 50 years, since the pr...
LTE-Advanced+Relay+Technology
LTE-Advanced becomes a truly global standard for 4G cellular communications. Relay, as one of the ke...
PLL锁相环
PLL(Phase Locked Loop)： 为锁相回路或锁相环，用来统一整合时钟信号，使高频器件正常工作，如内存的存取资料等。PLL用于振荡器中的反馈技术。 许多电子设备要正常工作，通常需要外部的...