搜索：PLI
找到约 8 项符合「PLI」的查询结果
结果 8
https://www.eeworm.com/dl/663/195555.html
VHDL/FPGA/Verilog
pli的文档资料
pli的文档资料，是cadence出的，详细介绍了pli的使用方法
https://www.eeworm.com/dl/663/266207.html
VHDL/FPGA/Verilog
vcs tutorial Lab2-PLI verygood
vcs tutorial Lab2-PLI verygood
https://www.eeworm.com/dl/663/145015.html
VHDL/FPGA/Verilog
VCS下编译通过的PLI的实例
VCS下编译通过的PLI的实例，包括功能仿真，和可综合代码
https://www.eeworm.com/dl/663/173534.html
VHDL/FPGA/Verilog
Verilog HDL的PLI子程序接口
Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，
https://www.eeworm.com/dl/534/172784.html
其他
pli_handbook_examples_pc verilog hdl 与C的接口的典型例子
pli_handbook_examples_pc
verilog hdl 与C的接口的典型例子
https://www.eeworm.com/dl/542/194896.html
其他书籍
Assertion based design_and:Including:Assertion methdology,Specifyingg RTL Properties, PLI-Based Ass
Assertion based design_and:Including:Assertion methdology,Specifyingg RTL Properties,
PLI-Based Assertions Functional coverage
https://www.eeworm.com/dl/647/292839.html
嵌入式/单片机编程
Analog signals are represented by 64 bit buses. They are converted to real and from real representa
Analog signals are represented by 64 bit buses. They are converted
to real and from real representation using PLI functions
https://www.eeworm.com/dl/900174.html
技术资料
Synopsys工具简介
VCS 是编译型Verilog 模拟器，它完全支持OVI 标准的Verilog HDL 语言、PLI 和SDF。VCS 具有目前行业中最高的模拟性能，其出色的内存管理能力足以支持千万门级的AS