波长信号的解调是实现光纤光栅传感网络的关键，基于现有的光纤光栅传感器解调方法，提出一种基于FPGA的双匹配光纤光栅解调方法，此系统是一种高速率、高精度、低成本的解调系统，并且通过引入双匹配光栅有效地克服了双值问题同时扩大了检测范围。分析了光纤光栅的测温原理并给出了该方案软硬件设计，综合考虑系统的解调精度和FPGA的处理速度给出了基于拉格朗日的曲线拟合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This PAPER analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this PAPER gives the curve fitting algorithm based on Lagrange.
上传时间： 2013-10-10
上传用户：zxc23456789
1.什么是CTP? CTP包括几种含义: 脱机直接制版(Computer-to-plate) 在机直接制版(Computer-to-press) 直接印刷(Computer-to-PAPER/print) 数字打样(Computer-to-proof) 普通PS版直接制版技术,即CTcP(Computer-to-conventional plate) 这里所论述的CTP系统是脱机直接制版(Computer-to-plate)。CTP就是计算机直接到印版，是一种数字化印版成像过程。CTP直接制版机与照排机结构原理相仿。起制版设备均是用计算机直接控制，用激光扫描成像，再通过显影、定影生成直接可上机印刷的印版。计算机直接制版是采用数字化工作流程，直接将文字、图象转变为数字，直接生成印版，省去了胶片这一材料、人工拼版的过程、半自动或全自动晒版工序。
标签： CTP
上传时间： 2014-01-22
上传用户：鱼哥哥你好
本文利用Verilog HDL 语言自顶向下的设计方法设计多功能数字钟，突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点，并通过Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成综合、仿真。此程序通过下载到FPGA 芯片后，可应用于实际的数字钟显示中。 关键词：Verilog HDL；硬件描述语言；FPGA Abstract: In this PAPER, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA
上传时间： 2013-11-10
上传用户：hz07104032
ref-sdr-sdram-vhdl代码 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White PAPER v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上传时间： 2013-10-23
上传用户：半熟1994
The revolution of automation on factory floors is a key driver for the seemingly insatiable demand for higher productivity， lower total cost of ownership，and high safety. As a result， industrial applications drive an insatiable demand of higher data bandwidth and higher system-level performance. This white PAPER describes the trends and challenges seen by designers and how FPGAs enable solutions to meet their stringent design goals.
上传时间： 2013-11-08
上传用户：yan2267246
在Multisim 10软件环境下，设计一种由运算放大器构成的精确可控矩形波信号发生器，结合系统电路原理图重点阐述了各参数指标的实现与测试方法。通过改变RC电路的电容充、放电路径和时间常数实现了占空比和频率的调节，通过多路开关投入不同数值的电容实现了频段的调节，通过电压取样和同相放大电路实现了输出电压幅值的调节并提高了电路的带负载能力，可作为频率和幅值可调的方波信号发生器。Multisim 10仿真分析及应用电路测试结果表明，电路性能指标达到了设计要求。 Abstract: Based on Multisim 10， this PAPER designed a kind of rectangular-wave signal generator which could be controlled exactly composed of operational amplifier， the key point was how to implement and test the parameter indicators based on the circuit diagram. The duty and the frequency were adjusted by changing the time constant and the way of charging and discharging of the capacitor， the width of frequency was adjusted by using different capacitors provided with multiple switch， the amplitude of output voltage was adjusted by sampling voltage and using in-phase amplifier circuit，the ability of driving loads was raised， the circuit can be used as squarewave signal generator whose frequency and amplitude can be adjusted. The final simulation results of Multisim 10 and the tests of applicable circuit show that the performance indicators of the circuit meets the design requirements.
上传时间： 2014-01-21
上传用户：shen007yue
结合均匀设计表和小边经验公式产生初始种群，使TSP应用遗传算法能求出更优更快解，详尽说明见PAPER.doc。
上传时间： 2013-12-24
上传用户：虫虫虫虫虫虫
The code assumes a two-dimensional computational domain with TMz polarization (i.e., non-zero field Ez, Hx, and Hy). The program is currently written so that the incident field always strikes the lower-left corner of the total-field region first. (If you want a different corner, that should be a fairly simple tweak to the code, but for now you ll have to make that tweak yourself.) I have attempted to provide copious comments in the code and hope that a knowledgeable C programmer can quickly map the approach as described in the PAPER to what is in the program.
标签： two-dimensional computational polarization non-zero
上传时间： 2013-12-13
上传用户：cylnpy
The tar file contains the following files: ptfsf.c: heart of the perfect TFSF code ptfsf.h: header file for same ptfsf-demo.c: FDTD code which demonstrates use of perfect TFSF code. Essentially this program used to generate results shown in the PAPER ptfsf-file-maker.c: code to generate an incident-field file using the "perfect" incident fields ptfsf-demo-file.c: FDTD code which uses the perfect incident fields stored in a file fdtdgen.h: defines macros used in much of my code Makefile: simple make-file to compile programs Also include are some simple script files to run the programs with reasonable values. The code assumes a two-dimensional computational domain with TMz polarization (i.e., non-zero field Ez, Hx, and Hy). The program is currently written so that the incident field always strikes the lower-left corner of the total-field region first. (If you want a different corner, that should be a fairly simple tweak to the code, but for now you ll have to make that tweak yourself.)
标签： ptfsf following the contains
上传时间： 2013-11-28
上传用户：风之骄子
This set of simulation files performs a computational complexity performance comparison of the two methods mentioned in the PAPER. The source is ANSI-C compliant, hence any C-compiler can be used to compile the source code. It has been tested using Visual Studio.net C++ and TI code composer studio C compiler for the TMS320C6701. Note that the performance comparison may be different for different platforms.
标签： computational performance complexity comparison
上传时间： 2014-12-22
上传用户：aig85
