ICCAVR简介ICCAVR 是一种使用ANSI 标准C 语言来开发微控制器（MCU）程序的一个工具，它是一个综合了编辑器和工程管理器的集成工作环境（IDE）。源文件全部被组织到工程之中，文件的编辑和工程（project）的构筑也在IDE 的环境中完成。编译错误在状态窗口中显示，用鼠标单击编译错误时，光标会自动跳转到出错行。这个工程管理器还能直接产生INTEL HEX格式的烧写文件和可以在AVR Studio 中调试的COFF 格式的调试文件。这里特别要提一下ICCAVR 中的应用构筑向导，可以在Tools 栏中选择“ApplicationBiulder”或者直接点击快捷工具栏中的“Application Biulder”图标，就可以打开应用构筑向导对话框，可以根据需要设定芯片种类，各个端口初始值，是否使用定时器，中断，UART等，选好以后单击“OK”就可以得到所需的硬件初始化程序段，非常可靠而且方便。图1给出了初始化UART 的一个例子：下面介绍一下创建并编译一个工程文件的简要步骤：1．新建一个源文件从file 菜单中选择new，创建一个新文件，在改文件中输入源程序并进行编辑和修改，然后存盘，在存盘时必须指定文件类型，如命名为：try.c 。写一个新文件的步骤：首先用Biulder 初始化需要用到的硬件资源，生成初始化程序，然后再写需要的代码实现所要的功能。2．新建一个project从projrct 菜单中选择new 命令，IDE 会弹出一个对话框，在对话框中用户可以指定工程存放的文件夹和工程的名称。在建立一个新工程之后，在工程管理器的窗口会出现三个子目录，Files, Headers, Documents,这时就可以将要编译的文件添加到project 中了。3．把文件添加到工程中可以在project-files 里单击右键，选择需要添加的文件；也可以在编辑窗口中单击右键选择弹出窗口的“Add To Project”命令。4．编译源文件在编译之前特别要注意在Project Options 中选择与硬件相应的芯片。如本次实验就选择ATMEGA8515,如图2 所示。在project 中选择make project,也可以直接单击快捷键F9，这时要是有错则会弹出出错信息，修改调试正确以后单击快捷键ISP 就可以烧写到硬件中去了。
标签： ICCAVR
上传时间： 2013-10-25
上传用户：569342831
The HCS12X family is the successor to the HCS12family, with many additional features. One new feature isthe increased memory available to the CPU and themethods available to access it. This document focuses onthe improved memory map configuration.
上传时间： 2013-11-13
上传用户：王者A
汇编器在微处理器的验证和应用中举足轻重，如何设计通用的汇编器一直是研究的热点之一。本文提出了一种开放式的汇编器系统设计思想，在汇编语言与机器语言间插入中间代码CMDL（code mapping description language）语言，打破汇编语言与机器语言的直接映射关系，由此建立起一套描述汇编语言与机器语言的开放式映射体系。基于此开放式映射体系开发了一套汇编器系统，具有较高层次上的通用性和可移植性。【关键词】指令集，CMDL，汇编器，开放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【关键词】instruction set, symbol table, assembler, lexical analysis, retargetability
上传时间： 2013-10-10
上传用户：meiguiweishi
Keil uVision3下载:keil uvision3注册机，keil uvision3中文版:Keil uVision3软件破解版与没破解版的区别就是一个没有代码限制，一个有2K代码限制。附件含有手册和教程。 1.点击c51v802.exe直接安装直到结束，安装路径最好选用默认的c:\keil与 原来的老板本放到相同的目录下会自动添加一个新的目录c:\keil\uv3 2.第一次运行请先进入file->License Management弹出窗口下输入注册码， 注册码由Keil_lic_v2.exe生成，选择V2选项，生成后复制LIC0内容到keil 弹出窗口的New License ID Code中然后点击Add LIC,注意看看注册后的使 用期限，如果太短可以用注册机重新生成，一般都可以找到30年左右:-) 3.复制ccKeilVxx.exe文件到c:\keil\c51\bin\下面并运行，以修正0xFD BUG. 至此安装完毕。
上传时间： 2013-10-14
上传用户：ruixue198909
The 87C576 includes two separate methods of programming theEPROM array, the traditional modified Quick-Pulse method, and anew On-Board Programming technique (OBP).Quick Pulse programming is a method using a number of devicepins in parallel (see Figure 1) and is the traditional way in which87C51 family members have been programmed. The Quick-Pulsemethod supports the following programming functions:– program USER EPROM– verify USER EPROM– program KEY EPROM– program security bits– verify security bits– read signature bytesThe Quick-Pulse method is quite easily suited to standardprogramming equipment as evidenced by the numerous vendors of87C51 compatible programmers on the market today. Onedisadvantage is that this method is not well suited to programming inthe embedded application because of the large number of signallines that must be isolated from the application. In addition, parallelsignals from a programmer would need to be cabled to theapplication’s circuit board, or the application circuit board wouldneed to have logic built-in to perform the programming functions.These requirements have generally made in-circuit programmingusing the modified Quick Pulse method impractical in almost all87C51 family applications.
上传时间： 2013-10-21
上传用户：xiaozhiqban
摘 要:用一种新的思路和方法,先计算低通、再计算高通滤波器的有关参数,然后组合成带通滤波器.关键词:滤波器;参数;新思路中图分类号: TN713. 5 文献识别码:B 文章编号:1008 - 1666 (1999) 04 - 0089 - 03A New Consideration of the Band Filter’s CalculationGuo Wencheng( S hao Yang B usiness and Technology school , S haoyang , Hunan ,422000 )Abstract :This essay deals with a new method of calculating the band filters - first calculatingthe relevant parameters of low - pass filters ,then calculating the ones of high - pass filters.Key words :filter ; parameters ;new considercation八十年代后,信息产业得到了迅猛发展. 带通滤波器在微波通信、广播电视和精密仪器设备中得到了广泛应用. 带通滤波器性能的优劣,对提高接收机信噪比,防止邻近信道干扰,提高设备的技术指标,有着十分重要的意义.我在长期的教学实践中,用切比雪夫型方法设计、计算出宽带滤波器集中参数元件的数据. 该滤波器可运用在检测微波频率的仪器和其他设备中. 再将其思路和计算方法介绍给大家,供参考.
上传时间： 2014-12-28
上传用户：Yukiseop
dsp
上传时间： 2013-10-10
上传用户：会稽剑客
在综合分析谐波励磁无刷同步发电机励磁控制系统的基础上,对其励磁控制策略进行了研究,开发了一套基于DSP( TMS320F2812) 控制的新型柴油发电机励磁控制系统,该系统采用参数自适应模糊PID 控制励磁,选用交流采样方式实时检测各信号的瞬时特性,系统仿真结果以及在1 台25 kW 工频柴油发电机上的试验结果证明了该控制器具有较好的电压调节特性,系统稳态和暂态性能完全满足发电机对励磁系统的要求。关键词:励磁调节;模糊PID 控制;数字信号处理器;交流采样 Abstract :According to the general analysis of the excitation cont rol system of the harmonious wave excitation brushless synchronous generator and it s characteristics ,a new type of diesel generator excitation cont rol system based on DSP( TMS320F2812) was designed. An adaptive fuzzy PID cont rol of excitation is used in this system. To detect the t ransient characteristics of the signals in a timely manner ,AC sampling was applied.The system simulation result s and the testing result s f rom a 25 kW diesel generator (50 Hz) can prove that the voltage regulation characteristics of the excitation cont rol system are very well ,and both the steadyOstate performance and the t ransient performance of the generator are also good.Key words :excitation cont rol ;fuzzy PID cont rol ;digital signal processor (DSP) ;AC sampling
上传时间： 2013-10-29
上传用户：fxf126@126.com
CCStudio Platinum Edition is available in a number of ways. Existingcustomers who are up-to-date with their subscription service withTexas Instruments will receive their update automatically on a CD inthe mail. New customers who wish to purchase a copy of CCStudioPlatinum Edition can order TMDSCCSALL-1 starting May 23, 2005. A120-day Trial version will be also be available on CDROM startingJuly 11, 2005. Users may order the CDROM of the 120-day free copy
上传时间： 2014-12-28
上传用户：gououo
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
