Multiple Coherehence simulate using matlab
标签： Coherehence Multiple simulate matlab
上传时间： 2014-12-07
上传用户：66666
b-树的增加,因为我看到的资料里的最大关键字数目为m-1,我考虑了一下,2-3树的删除会比较麻烦,后来看了下算法导论,别人的数目是2t-1,所以相同情况下是2-3-4树,我考虑按照这个因子再写一个,增加删除部分,有问题可以联系我,联系方式在程序中已注明.
上传时间： 2017-04-04
上传用户：pkkkkp
一个报税管理系统AJAX第二版B-S.rar
上传时间： 2014-01-10
上传用户：qw12
b-树的增加,删除,已对八百万个数据进行过测试,而且是对多个M值
上传时间： 2014-01-17
上传用户：nairui21
Udptalk is the first version to test multiple clients against one server...
标签： multiple Udptalk clients against
上传时间： 2017-04-07
上传用户：franktu
c pgm to find redundant paths in a graph.Many fault-tolerant network algorithms rely on an underlying assumption that there are possibly distinct network paths between a source-destination pair. Given a directed graph as input, write a program that uses depth-first search to determine all such paths. Note that, these paths are not vertex-disjoint i.e., the vertices may repeat but they are all edge-disjoint i.e., no two paths have the same edges. The input is the adjacency matrix of a directed acyclic graph and a pair(s) of source and destination vertices and the output should be the number of such disjoint paths and the paths themselves on separate lines. In case of multiple paths the output should be in order of paths with minimum vertices first. In case of tie the vertex number should be taken in consideration for ordering.
标签： fault-tolerant algorithms redundant underlyin
上传时间： 2013-12-18
上传用户：jkhjkh1982
Hi guys, I have a B-spline curve algorithm by using Genetic algorithm. Any interested?
标签： algorithm interested B-spline Genetic
上传时间： 2017-04-13
上传用户：shawvi
contains documents related to adaptive beamforming algorithms for Wideband Code Division multiple access and a research article on circular patch antenna for C band altimeter system
标签： beamforming algorithms documents contains
上传时间： 2014-09-04
上传用户：youlongjian0
B-M 算法的matlab实现 密码学中又一重要的算法实现
上传时间： 2017-04-18
上传用户：二驱蚊器
The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache with a write-invalidate policy. The L2 cache is two-way set associative, with a block size of 8 words, and a total capacity of 512 words.
标签： implementation instruction multiple purpose
上传时间： 2017-04-18
上传用户：731140412
