Modelsim
Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口...
资源总数
257
Modelsim 全部资料 257 份
通过文件读写方式实现Matlab和Modelsim的联合仿真
在FPGA进行算法验证的时候，经常需要输入仿真数据，这些数据可以用FPGA产生，但是如果数据产生过程很复杂的话，需要耗费很大的精力，并且产生的数据的准确性也不能保证。
2013-10-10
64
it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x
it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i hav...
2017-03-22
138
it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xin
it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have ...
2014-01-10
67
it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8
it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it...
2014-06-26
132