Microsoft+Hyper-V 源代码

module latch_8(qout,data,clk); output[7:0] qout; input[7:0] data; input clk; reg[7:0] qout; always @(clk or data) begin i…

module reg8(out_data,in_data,clk,clr); output[7:0] out_data; input[7:0] in_data; input clk,clr; reg[7:0] out_data; always @…

`include "adder.v" module adder16(cout,sum,a,b,cin); output cout; parameter my_size=16; output[my_size-1:0] sum; input[my_s…

`timescale 10ns/1ns module wave2; reg wave; parameter cycle=5; initial fork wave=0; #(cycle) wave=1; #(2*cycle)…

module voter7(pass,vote); output pass; input[6:0] vote; reg[2:0] sum; integer i; reg pass; always @(vote) begin sum=0; …

module count60(qout,cout,data,load,cin,reset,clk); output[7:0] qout; output cout; input[7:0] data; input load,cin,clk,reset; …

module loop1; integer i; initial for(i=0;i

module decode4_7(decodeout,indec); output[6:0] decodeout; input[3:0] indec; reg[6:0] decodeout; always @(indec) begin …

module MUX21_1(out,a,b,sel); input a,b,sel; output out; assign out=(sel==0)?a:b; endmodule

`timescale 10ns/1ns module wave1; reg wave; parameter cycle=10; initial begin wave=0; #(cycle/2) wave=1; #(…