Microsoft+Hyper-V 源代码

module mux4_1(out,in0,in1,in2,in3,sel); output out; input in0,in1,in2,in3; input[1:0] sel; reg out; always @(in0 or in1 or in…

module loop2; integer i; initial begin i=0; while(i

module loop3; integer i; initial begin i=0; repeat(4) begin $display ("i=%h",i); i=i+1; end end endmodule

module MUX21_2(out,a,b,sel); input a,b,sel; output out; reg out; always@(a or b or sel) begin if(sel==0) out=a; …

module paral1(q,a,clk); output q,a; input clk; reg q,a; always @(posedge clk) begin q=~q; end always @(posedge clk) b…

module code_83(din,dout); input[7:0] din; output[2:0] dout; function[2:0] code; input[7:0] din; casex (din) 8'b1xxx_xxxx :…

module serial2(q,a,clk); output q,a; input clk; reg q,a; always @(posedge clk) begin a=~q; q=~q; end endmodule

module paral2(q,a,clk); output q,a; input clk; reg q,a; always @(posedge clk) begin a=~q; end always @(posedge clk) b…

module serial1(q,a,clk); output q,a; input clk; reg q,a; always @(posedge clk) begin q=~q; a=~q; end endmodule

module full_add5(a,b,cin,sum,cout); input a,b,cin; output sum,cout; reg cout,m1,m2,m3; //在always块中被赋值的变量应定义为reg型 wire…