Microsoft Hyper-V 源代码

module counter4(clk,reset,q); input clk,reset; output q; reg[3:0]q; always @(posedge clk) begin if(!reset) q

module adder4(a,b,cin,sum,cout); output [3:0] sum; output cout; input [3:0] a,b; input cin; assign {cout,sum}=a+b+cin; e…

module div16(clk,rst,clk_16); input clk,rst; output clk_16; reg[3:0] count; always @(posedge clk or negedge rst) begin …

module Booth16(CLK, RESET, A, B, P); parameter WIDTH = 16; input CLK, RESET; input [WIDTH-1:0]A, B; output [WIDTH+WIDTH-1:0]…

module SEG7_LUT_8 ( oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG ); input [31:0] iDIG; output [6:0] oSEG0,oSEG1,oSEG2,oS…

// megafunction wizard: %ALTCLKLOCK% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: altpll // =======================…

/*****************************************/ /** 8bit RISC MCU desing **/ /** sel_tmp2 module **…

`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: NUDT //…

// -*- Mode: Verilog -*- // Filename : code_gen.v // Description : Generates early promp…

//------------------------------------------------------------------------------ // This confidential and proprietary software ma…