sel_tmp2.v

来自「此代码可用modelsim进行仿真」· Verilog 代码 · 共 18 行

/*****************************************/
/**        8bit RISC MCU desing         **/
/**          sel_tmp2 module            **/
/**            BY yuzhijie              **/
/**            2006.10.30               **/
/*****************************************/
`timescale 1ns/100ps
module sel_tmp2(sel_imm,ram_out,literalk,tmp2);
    //sel_imm :select ram_out or literal_out
    //ram_out :output of ram
    //literal :literal output
    //tmp2 : the second input of alu
    input sel_imm;
    input[7:0]ram_out,literalk;
    output[7:0]tmp2;
    assign tmp2=sel_imm?ram_out:literalk;
endmodule