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Low-Pin

  • Arduino应用_Arduino连接超声波传感器测距

    超声波传感器适用于对大幅的平面进行静止测距。普通的超声波传感器测距范围大概是 2cm~450cm,分辨率3mm(淘宝卖家说的,笔者测试环境没那么好,个人实测比较稳定的 距离10cm~2m 左右,超过此距离就经常有偶然不准确的情况发生了,当然不排除笔者技术 问题。) 测试对象是淘宝上面最便宜的SRF-04 超声波传感器,有四个脚:5v 电源脚(Vcc),触发控制端(Trig),接收端(Echo),地端(GND) 附:SRF 系列超声波传感器参数比较   模块工作原理: 采用IO 触发测距,给至少10us 的高电平信号; 模块自动发送8个40KHz 的方波,自动检测是否有信号返回; 有信号返回,通过IO 输出一高电平,高电平持续的时间就是超声波从发射到返回的时间.测试距离=(高电平时间*声速(340m/s))/2; 电路连接方法   Arduino 程序例子: constintTrigPin = 2; constintEchoPin = 3; floatcm; voidsetup() { Serial.begin(9600); pinMode(TrigPin, OUTPUT); pinMode(EchoPin, INPUT); } voidloop() { digitalWrite(TrigPin, LOW); //低高低电平发一个短时间脉冲去TrigPin delayMicroseconds(2); digitalWrite(TrigPin, HIGH); delayMicroseconds(10); digitalWrite(TrigPin, LOW); cm = pulseIn(EchoPin, HIGH) / 58.0; //将回波时间换算成cm cm = (int(cm * 100.0)) / 100.0; //保留两位小数 Serial.print(cm); Serial.print("cm"); Serial.println(); delay(1000); }

    标签: Arduino 连接 超声波传感器

    上传时间: 2013-10-18

    上传用户:星仔

  • superpro 3000u 驱动及编程器软件下载

    superpro 3000u 驱动 PIC16C65B@QFP44 [SA245] PIC16C65B:          Part number QFP44:              Package in QFP44 SA245:              Adapter purchase number AM29DL320GT@FBGA48 [SA642+B026] AM29DL320GT:        Part number FBGA48:             Package in FBGA48 SA642:              Adapter purchase number (Top board with socket) B026:               Adapter purchase number (Bottom board, exchangable for different parts) 87C196CA@PLCC68(universal adapter) [PEP+S414T] 87C196CA:           Part number PLCC68:             Package in PLCC68 universal adapter:  this adapter is valid for all parts in this package PEP:                The PEP (Pin-driver Expansion Pack necessary to work with the adapter S414T) S414T:              Adapter purchase number (Universal for all parts in this package) S71PL127J80B@FBGA64(special adapter) [(SA642A-B079A-Y096AF001)] S71PL127J80B:            Part number FBGA64:                  Package in FBGA64 special adapter:         this adapter is valid for this

    标签: superpro 3000u 驱动 编程器软件

    上传时间: 2013-10-23

    上传用户:Avoid98

  • Allegro FPGA System Planner中文介绍

      完整性高的FPGA-PCB系统化协同设计工具   Cadence OrCAD and Allegro FPGA System Planner便可满足较复杂的设计及在设计初级产生最佳的I/O引脚规划,并可透过FSP做系统化的设计规划,同时整合logic、schematic、PCB同步规划单个或多个FPGA pin的最佳化及layout placement,借由整合式的界面以减少重复在design及PCB Layout的测试及修正的过程及沟通时间,甚至透过最佳化的pin mapping、placement后可节省更多的走线空间或叠构。   Specifying Design Intent   在FSP整合工具内可直接由零件库选取要摆放的零件,而这些零件可直接使用PCB内的包装,预先让我们同步规划FPGA设计及在PCB的placement。  

    标签: Allegro Planner System FPGA

    上传时间: 2013-10-19

    上传用户:shaojie2080

  • 使用Artix-7 FPGA 降低您的系统功耗与成本

    As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-sensitive markets. Application classes like

    标签: Artix FPGA 功耗

    上传时间: 2013-11-08

    上传用户:immanuel2006

  • PADS Layout把非中心对称封装的元件坐标导出所修改的Basic Scr

    有时候,做元件封装的时候,做得不是按中心设置为原点(不提倡这种做法),所以制成之后导出来的坐标图和直接提供给贴片厂的要求相差比较大。比如,以元件的某一个pin 脚作为元件的原点,明显就有问题,直接修改封装的话,PCB又的重新调整。所以想到一个方法:把每个元件所有的管脚的X坐标和Y坐标分别求平均值,就为元件的中心。

    标签: Layout Basic PADS Scr

    上传时间: 2014-01-09

    上传用户:xzt

  • Create a 1-Wire Master with Xilinx PicoBlaze

    Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.

    标签: PicoBlaze Create Master Xilinx

    上传时间: 2013-11-12

    上传用户:大三三

  • protel 99se 使用技巧以及常见问题解决方法

    protel 99se 使用技巧以及常见问题解决方法:里面有一些protel 99se 特别技巧,还有我们经常遇到的一些问题!如何使一条走线至两个不同位置零件的距离相同? 您可先在Design/Rule/High Speed/Matched Net Lengths的规则中来新增规则设定,最后再用Tools/EqualizeNet Lengths 来等长化即可。 Q02、在SCHLIB中造一零件其PIN的属性,如何决定是Passive, Input, I/O, Hi- Z,Power,…..?在HELP中能找到说明吗?市面有关 SIM?PLD?的书吗?或贵公司有讲义? 你可在零件库自制零件时点选零件Pin脚,并在Electrical Type里,可以自行设定PIN的 属性,您可参考台科大的Protel sch 99se 里面有介绍关于SIM的内容。 Q03、请问各位业界前辈,如何能顺利读取pcad8.6版的线路图,烦请告知 Protel 99SE只能读取P-CAD 2000的ASCII档案格式,所以你必须先将P-CAD8.6版的格式转为P-CAD 2000的档案格式,才能让Protel读取。 Q04、请问我该如何标示线径大小的那个平方呢 你可以将格点大小设小,还有将字形大小缩小,再放置数字的平方位置即可。 Q05、请问我一次如何更改所有组件的字型 您可以点选其中一个组件字型,再用Global的方法就可以达成你的要求。

    标签: protel 99 se 使用技巧

    上传时间: 2015-01-01

    上传用户:yxgi5

  • 《器件封装用户向导》赛灵思产品封装资料

    Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.

    标签: 封装 器件 用户 赛灵思

    上传时间: 2013-11-21

    上传用户:不懂夜的黑

  • Analog Solutions for Altera FPGAs

    Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)

    标签: Solutions Analog Altera FPGAs

    上传时间: 2013-10-27

    上传用户:fredguo

  • Analog Solutions for Xilinx FPGAs

    Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables

    标签: Solutions Analog Xilinx FPGAs

    上传时间: 2013-11-07

    上传用户:suicone