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LDPC Decoder for rate=1/2 Min-Sum, Sum-Product, Scaling Min-Sum Layered Decoding for Matlab Code
DAC outputs a sine wave 550Hz to DAC0. Rate calculations assume defualt clock of 2.097152MHz 针对于ADUC848
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static c...
Generate trellis data of a rate-1/n convolutional encoder.卷积码1/n的编码器，注意生成的是非系统码。
51单片机中的波特率发生器51 single-chip baud rate generator in
：some examples of assembler level programming for the ARM（produces an ELF executable file which can be loaded into an AR...
《Debugging with GDB--The GNU Source-Level Debugger》 9th Edition 2004 By Richard Stallman,Roland Pesch,Stan Shebs F...
IEEE Std 1364.1-2002 IEEE Std. 1364.1 - 2002 IEEE Standard for Verilog Register Transfer Level Synthesis.rar
Mitigation of Non-linear Distortion Using PTS and IDAR Method for Multi-Level QAM-OFDM System
This the first release (version 0.0) of the Peersim high level P2P network simulator. This archive contains the java...