VHDL code for a clock divider by 27 circuit with a resulting waveform with 50% duty cycle..
VHDL code for a clock divider by 27 circuit with a resulting waveform with 50% duty cycle..
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VHDL code for a clock divider by 27 circuit with a resulting waveform with 50% duty cycle..
this source code for displayed clock & alarm in 2*16 LCD and writed in codevisionAVR for useable AVR mcu
This is the source code of a digital clock implemented using Atmel 8 bit AVR Controller(ATMega16). To fully understand i...
DAC outputs a sine wave 550Hz to DAC0. Rate calculations assume defualt clock of 2.097152MHz 针对于ADUC848
This zip file describes how to generate a clock on the PCK pin using the PMC running under AT91RM3400DK with Green hills...
c8051f020 实时时钟模块程序 内含IIC模块程序/********************** SYSTEM CLOCK 8M********************************/ extern unsigned ch...
A sample C program to demonstrate the usage of rtc() function in Linux to read the read time clock.
This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the S...
pcf8593实时时钟的驱动实例 Real Time Clock interface for Linux on CPE with FTRTC010