This diskette (version 1.0) contains demonstration programs and source codes in MATLAB (v.5.2) for algorithms listed in the textbook Global Positioning Systems, Inertial Navigation, and Integration, by M. S. Grewal, Lawrence Weill, and A. P. Andrews, published by John Wiley and Sons, 2000. Contents: MATLAB (Version 5.2) Demonstrations & Scripts Chapter4 ephemeris.m calculates the GPS satellite position in ECEF coordinates from its ephemeris parameters. Chapter5 Klobuchar_fix.m calculates the ionospheric delay. Chapter6 (shows the quaternion utilities)
标签： demonstration diskette contains programs
上传时间： 2016-10-20
上传用户：坏天使kk
个人所得税计算器 v个人所得税计算器
标签： 计算器
上传时间： 2014-01-23
上传用户：bibirnovis
detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.
标签： FPGA programming for reference
上传时间： 2013-11-30
上传用户：a673761058
detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.
标签： FPGA programming for reference
上传时间： 2016-10-23
上传用户：pkkkkp
detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.
标签： FPGA programming for reference
上传时间： 2013-12-20
上传用户：zhangyi99104144
MATLAB C/C++ Math Library v2 und API (Application Programm Interface)
标签： Application Interface Programm Library
上传时间： 2016-10-25
上传用户：fandeshun
Discription: This multi-master driver provides the software interface to the I2C Bus hardware of the M3062x series of MitsubishiMCU.
标签： multi-master Discription interface the
上传时间： 2016-10-28
上传用户：ljt101007
Atmel mcu can interface design example
标签： interface example design Atmel
上传时间： 2016-10-30
上传用户：yimoney
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2013-12-13
上传用户：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2014-01-20
上传用户：三人用菜
