A thesis on developing multiple-precision INTEGER libraries for cryptographic and other uses.
标签： multiple-precision cryptographic developing libraries
上传时间： 2014-01-10
上传用户：xiaohuanhuan
关于FPGA流水线设计的论文\r\nThis work investigates the use of very deep pipelines for\r\nimplementing circuits in FPGAs, where each pipeline\r\nstage is limited to a single FPGA logic element (LE). The\r\narchitecture and VHDL design of a parameterized INTEGER\r\na
上传时间： 2013-09-03
上传用户：wl9454
The MAX2870 ultra-wideband phase-locked loop (PLL) and voltagecontrol oscillator (VCO) can operate in both INTEGER-N and fractional-Nmodes, similar to the Analog Devices ADF4350 wideband synthesizer.This application note compares the MAX2870 and ADF4350 registers andloop filter design in detail. Users who already familiar with ADF4350 canuse this application note as a quick design reference.
上传时间： 2014-12-23
上传用户：变形金刚
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus INTEGER multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
上传时间： 2013-11-11
上传用户：pans0ul
本文简单探讨了verilog HDL设计中的可综合性问题，适合HDL初学者阅读 用组合逻辑实现的电路和用时序逻辑实现的 电路要分配到不同的进程中。 不要使用枚举类型的属性。 INTEGER应加范围限制。 通常的可综合代码应该是同步设计。 避免门级描述，除非在关键路径中。
上传时间： 2013-10-21
上传用户：smallfish
Analog Inputs and Outputs in an S7 PLC are represented in the PLC as a 16-bit INTEGER. Over the nominal span of the analog input or output, the value of this INTEGER will range between - 27648 and +27648. However, it is easier to use the analog values if they are scaled to the same units and ranges as the process being controlled. This applications tip describes methods for scaling analog values to and from engineering units.
上传时间： 2013-11-17
上传用户：3294322651
MPLAB C30用户指南(英文) HIGHLIGHTSThe information covered in this chapter is as follows:• About this Guide• Recommended Reading• Troubleshooting• The Microchip Web Site• Development Systems Customer Notification Service• Customer Support Document LayoutThe document layout is as follows:• Chapter 1: Compiler Overview – describes MPLAB C30, development tools andfeature set.• Chapter 2: Differences between MPLAB C30 and ANSI C – describes thedifferences between the C language supported by MPLAB C30 syntax and thestandard ANSI-89 C.• Chapter 3: Using MPLAB C30 – describes how to use the MPLAB C30 compilerfrom the command line.• Chapter 4: MPLAB C30 Runtime Environment – describes the MPLAB C30runtime model, including information on sections, initialization, memory models, thesoftware stack and much more.• Chapter 5: Data Types – describes MPLAB C30 INTEGER, floating point and pointerdata types.• Chapter 6: Device Support Files – describes the MPLAB C30 header and registerdefinition files, as well as how to use with SFR’s.• Chapter 7: Interrupts – describes how to use interrupts.• Chapter 8: Mixing Assembly Language and C Modules – provides guidelines tousing MPLAB C30 with MPLAB ASM30 assembly language modules.
上传时间： 2013-10-21
上传用户：13925096126
状态机设计:8.1.1 数据类型定义语句TYPE语句的用法如下：TYPE 数据类型名IS 数据类型定义OF 基本数据类型;或TYPE 数据类型名IS 数据类型定义;TYPE st1 IS ARRAY ( 0 TO 15 ) OF STD_LOGIC ;TYPE week IS (sun，mon，tue，wed，thu，fri，sat) ; 8.1.1 数据类型定义语句TYPE m_state IS ( st0，st1，st2，st3，st4，st5 ) ;SIGNAL present_state，next_state : m_state ;TYPE BOOLEAN IS (FALSE，TRUE) ；TYPE my_logic IS ( '1' ，'Z' ，'U' ，'0' ) ;SIGNAL s1 : my_logic ;s1 <= 'Z' ;SUBTYPE 子类型名IS 基本数据类型RANGE 约束范围;SUBTYPE digits IS INTEGER RANGE 0 to 9 ;
标签： 状态
上传时间： 2013-11-05
上传用户：nem567397
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, INTEGER data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上传时间： 2013-10-08
上传用户：18711024007
各种功能的计数器实例（VHDL源代码）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;
上传时间： 2014-11-30
上传用户：半熟1994
