This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assumi
This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assumi...
This example sets up the PLL in x10/2 mode, divides SYSCLKOUT by six to reach a 25Mhz HSPCLK (assumi...