这一节的目的是使用XPS为ARM PS 处理系统 添加额外的IP。从IP Catalog 标签添加GPIO，并与ZedBoard板子上的8个LED灯相连。当系统建立完后，产生bitstream，并对外设进行测试。本资料为源代码，原文设计过程详见：【 玩转赛灵思Zedboard开发板（4）：如何使用自带外设IP让ARM PS访问FPGA？】 硬件平台：Digilent ZedBoard 开发环境：Windows XP 32 bit 软件： XPS 14.2 +SDK 14.2
上传时间： 2013-11-06
上传用户：yuchunhai1990
Arduino，是一块基于开放源代码的USB接口Simple i/o接口板（包括12通道数字GPIO，4通道PWM输出，6-8通道10bit ADC输入通道），并且具有使用类似Java,C语言的IDE集成开发环境。 让您可以快速使用Arduino语言与Flash或Processing…等软件，作出互动作品。 Arduino可以使用开发完成的电子元件例如Switch或sensors或其他控制器、LED、步进马达或其他输出装置。Arduino也可以独立运作成为一个可以跟软件沟通的接口，例如说：flash、processing、Max/MSP、VVVV 或其他互动软件…。Arduino开发IDE接口基于开放源代码原，可以让您免费下载使用开发出更多令人惊艳的互动作品。 特色： 1、开放源代码的电路图设计，程序开发接口免费下载，也可依需求自己修改。 2、使用低价格的微处理控制器(ATMEGA8或ATmega128)。可以采用USB接口供电，不需外接电源。也可以使用外部9VDC输入 3、Arduino支持ISP在线烧，可以将新的“bootloader”固件烧入ATmega8或ATmega128芯片。有了bootloader之后，可以通过串口或者USB to Rs232线更新固件。 4、可依据官方提供的Eagle格式PCB和SCH电路图，简化Arduino模组，完成独立运作的微处理控制。可简单地与传感器，各式各样的电子元件连接(EX：红外线,超音波,热敏电阻,光敏电阻,伺服马达,…等) 5、支持多种互动程序，如：Flash、Max/Msp、VVVV、PD、C、Processing……等 6、应用方面，利用Arduino，突破以往只能使用鼠标，键盘，CCD等输入的装置的互动内容，可以更简单地达成单人或多人游戏互动。
标签： Arduino
上传时间： 2013-10-17
上传用户：cuiyashuo
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
上传时间： 2013-11-11
上传用户：zwei41
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2014-11-26
上传用户：erkuizhang
Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.
上传时间： 2013-10-22
上传用户：lmq0059
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
标签： CPLD
上传时间： 2014-12-05
上传用户：qazxsw
波长信号的解调是实现光纤光栅传感网络的关键，基于现有的光纤光栅传感器解调方法，提出一种基于FPGA的双匹配光纤光栅解调方法，此系统是一种高速率、高精度、低成本的解调系统，并且通过引入双匹配光栅有效地克服了双值问题同时扩大了检测范围。分析了光纤光栅的测温原理并给出了该方案软硬件设计，综合考虑系统的解调精度和FPGA的处理速度给出了基于拉格朗日的曲线拟合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
上传时间： 2013-10-10
上传用户：zxc23456789
各种功能的计数器实例（VHDL源代码）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;
上传时间： 2013-10-09
上传用户：松毓336
试目的LPC1114在深度睡眠模式下，采用低频看门狗时钟作为系统，开启定时器，实现控制器的周期性唤醒，以及此方案下的功耗测试。注：由于LPC1114在深度睡眠模式下只能通过13个GPIO引脚进行唤醒（PIO0_0 ~ PIO0_11和PIO1_0），但是在很多应用场合需要使用定时器周期性唤醒CPU，本测试既是针对此需求提出一种解决方案。
上传时间： 2013-11-08
上传用户：mqien
电子发烧友网：本资料是关于单片机及接口技术这门课程的期末考试试卷及答案的详解。 8.当需要从MCS-51单片机程序存储器取数据时，采用的指令为( )。 a)MOV A, @R1 b)MOVC A, @A + DPTR c)MOVX A, @ R0 d)MOVX A, @ DPTR 二、填空题(每空1分，共30分) 1.一个完整的微机系统由 和 两大部分组成。 2.8051 的引脚RST是____(IN脚还是OUT脚)，当其端出现____电平时,8051进入复位状态。8051一直维持这个值，直到RST脚收到____电平，8051才脱离复位状态，进入程序运行状态，从ROM H单元开始取指令并翻译和执行。 3.半导体存储器分成两大类 和 ，其中 具有易失性，常用于存储 。
上传时间： 2015-01-03
上传用户：wfl_yy
