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  • lpc2292/lpc2294 pdf datasheet

    The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.

    标签: lpc datasheet 2292 2294

    上传时间: 2014-12-30

    上传用户:aysyzxzm

  • Virtex-6 FPGA PCB设计手册

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.

    标签: Virtex FPGA PCB 设计手册

    上传时间: 2013-11-11

    上传用户:zwei41

  • XAPP806 -决定DDR反馈时钟的最佳DCM相移

    This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.

    标签: XAPP 806 DDR DCM

    上传时间: 2014-11-26

    上传用户:erkuizhang

  • CPLD库指南

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.  

    标签: CPLD

    上传时间: 2014-12-05

    上传用户:qazxsw

  • 采用高速串行收发器Rocket I/O实现数据率为2.5 G

    摘要: 串行传输技术具有更高的传输速率和更低的设计成本, 已成为业界首选, 被广泛应用于高速通信领域。提出了一种新的高速串行传输接口的设计方案, 改进了Aurora 协议数据帧格式定义的弊端, 并采用高速串行收发器Rocket I/O, 实现数据率为2.5 Gbps的高速串行传输。关键词: 高速串行传输; Rocket I/O; Aurora 协议 为促使FPGA 芯片与串行传输技术更好地结合以满足市场需求, Xilinx 公司适时推出了内嵌高速串行收发器RocketI/O 的Virtex II Pro 系列FPGA 和可升级的小型链路层协议———Aurora 协议。Rocket I/O支持从622 Mbps 至3.125 Gbps的全双工传输速率, 还具有8 B/10 B 编解码、时钟生成及恢复等功能, 可以理想地适用于芯片之间或背板的高速串行数据传输。Aurora 协议是为专有上层协议或行业标准的上层协议提供透明接口的第一款串行互连协议, 可用于高速线性通路之间的点到点串行数据传输, 同时其可扩展的带宽, 为系统设计人员提供了所需要的灵活性[4]。但该协议帧格式的定义存在弊端,会导致系统资源的浪费。本文提出的设计方案可以改进Aurora 协议的固有缺陷,提高系统性能, 实现数据率为2.5 Gbps 的高速串行传输, 具有良好的可行性和广阔的应用前景。

    标签: Rocket 2.5 高速串行 收发器

    上传时间: 2013-10-13

    上传用户:lml1234lml

  • USB接口控制器参考设计,xilinx提供VHDL代码 us

    USB接口控制器参考设计,xilinx提供VHDL代码 usb xilinx vhdl ;  This program is free software; you can redistribute it and/or modify ;  it under the terms of the GNU General Public License as published by ;  the Free Software Foundation; either version 2 of the License, or ;  (at your option) any later version. ;      ;  This program is distributed in the hope that it will be useful, ;  but WITHOUT ANY WARRANTY; without even the implied warranty of ;  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the ;  GNU General Public License for more details. ;      ;  You should have received a copy of the GNU General Public License ;  along with this program; if not, write to the Free Software ;  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

    标签: xilinx VHDL USB us

    上传时间: 2013-10-29

    上传用户:zhouchang199

  • 题目:利用条件运算符的嵌套来完成此题:学习成绩>=90分的同学用A表示

    题目:利用条件运算符的嵌套来完成此题:学习成绩>=90分的同学用A表示,60-89分之间的用B表示,60分以下的用C表示。 1.程序分析:(a>b)?a:b这是条件运算符的基本例子。

    标签: gt 90 运算符 嵌套

    上传时间: 2015-01-08

    上传用户:lifangyuan12

  • 用Java写的报表.功能如下: 0.内建网络打印,网络预览功能! 1.文件操作。包括url 指定的文件。 2.全功能打印支持。包括打印预览。 3.Undo 和 redo。 4.合并单元格。 5.Cel

    用Java写的报表.功能如下: 0.内建网络打印,网络预览功能! 1.文件操作。包括url 指定的文件。 2.全功能打印支持。包括打印预览。 3.Undo 和 redo。 4.合并单元格。 5.Cell selection using the mouse or keyboards(快捷键支持)。 6.单元格高宽调整 。 7.丰富的前景刷支持,前景可以是单色,双色渐变,JPG,PNG,GIF图形 。 8.背景刷支持,前景可以是单色,双色渐变,JPG,PNG,GIF图形 。 9.每个单元格支持空心字体,各其他一般字体。 10.每个单元格可设置为只读。 11.每个单元格上下左右可分别高设置边框,边框线的宽度,颜色可调。 12.拖放操作。可在一个应用中的不同单元格拖放,也可在两个应用的之间进行拖放。支持剪切和COPY两种方式。 13.剪贴板功能。支持文本方式和全格式两种方式。剪贴也允许在两个应用之间进行。可以从EXCELL单元格中复制到本应用中。 14.单元格线,滚动条,行头,列头显示可选. 15.支持公式定义,公式定义采用?作标记,如?sum(A1:B1)。 16.数字格式可自由定义,如 12345678, 可自动化为 12,345,678.00 。 17.丰富的页脚页眉属性。具有以上3,4,5,6?,8,9,10,11,12,13,15,16,17各项功能。

    标签: Java Undo redo Cel

    上传时间: 2015-03-15

    上传用户:熊少锋

  • 基于matlab的mp3的读写函数Mp3 toolbox for Matlab. Alfredo Fernandez Franco Aalborg University Departament of

    基于matlab的mp3的读写函数Mp3 toolbox for Matlab. Alfredo Fernandez Franco Aalborg University Departament of Acoustics M.Sc. Student aberserk@yahoo.com Includes 2 functions to write and read MP3 files. It works like the commands WAVWRITE and WAVREAD. 1.- Just unpack in the toolbox folder under the MATLAB directory. 2.- Set the MATLAB search path to include that folder. This version was made in MATLAB for WINDOWS only. I ll probably will make the UNIX version later. 01-11-2004.

    标签: Departament University Fernandez Alfredo

    上传时间: 2014-12-02

    上传用户:开怀常笑

  • RSA算法 :首先, 找出三个数, p, q, r, 其中 p, q 是两个相异的质数, r 是与 (p-1)(q-1) 互质的数...... p, q, r 这三个数便是 person_key

    RSA算法 :首先, 找出三个数, p, q, r, 其中 p, q 是两个相异的质数, r 是与 (p-1)(q-1) 互质的数...... p, q, r 这三个数便是 person_key,接著, 找出 m, 使得 r^m == 1 mod (p-1)(q-1)..... 这个 m 一定存在, 因为 r 与 (p-1)(q-1) 互质, 用辗转相除法就可以得到了..... 再来, 计算 n = pq....... m, n 这两个数便是 public_key ,编码过程是, 若资料为 a, 将其看成是一个大整数, 假设 a < n.... 如果 a >= n 的话, 就将 a 表成 s 进位 (s

    标签: person_key RSA 算法

    上传时间: 2013-12-14

    上传用户:zhuyibin