参照栈类模板的例子编写一个队列类模板class <T> Queue，私有成员包括：队首指针Front，队尾指针Tail，队列容积max。实现：构造函数Queue，复制构造函数Queue，析构函数~Queue，入队函数In，出队函数Out（每次出队，后面的元素自动前移一位），判队列空函数Empty。并分别用队列类模板定义int和double对象，通过实例调用各个成员函数。
标签： Queue 函数 double class Front Empty 队列 Tail 模板 Out
上传时间： 2020-05-04
上传用户：1qw2e3r4t5y6u7i8
Artificial Intelligence (AI) is a big field, and this is a big book. We have tried to explore the full breadth of the field, which encompasses logic, probability, and continuous mathematics; perception, reasoning, learning, and action; and everything from microelectronic devices to robotic planetary explorers. The book is also big because we go into some depth. The subtitle of this book is “A Modern Approach.” The intended meaning of this rather Empty phrase is that we have tried to synthesize what is now known into a common frame- work, rather than trying to explain each subfield of AI in its own historical context. We apologize to those whose subfields are, as a result, less recognizable.
标签： A-Modern-Approach Intelligence
上传时间： 2020-06-10
上传用户：shancjb
FPGA片内FIFO读写测试Verilog逻辑源码Quartus工程文件+文档说明，使用 FPGA 内部的 FIFO 以及程序对该 FIFO 的数据读写操作。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz时钟 input rst_n //复位信号，低电平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO写数据wire wr_en; //FIFO写使能wire rd_en; //FIFO读使能wire[15:0] r_data; //FIFO读数据wire full; //FIFO满信号 wire Empty; //FIFO空信号 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///产生FIFO写入的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(Empty == 1'b1) //FIFO空， 开始写FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO满 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///产生FIFO读的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO满, 开始读FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(Empty == 1'b1)
上传时间： 2021-12-19
上传用户：20125101110
一、建立基本的项目平台在建项目平台前需要做一些准备，选择一个盘建立 Platform”文件夹，在Platform"文件夹下建boot".HardWareTest"、"Project"、"Src"四个文件夹，boot"用来存放bootloader工程程序，HardWareTest"用来存放硬件自动测试工程程序，"Project"用来存放项目平台建立时生产的文件，"Src"用来存放STM32uCOSl工程的应用程序。下面开始建项目平台吧。步骤一：新建一个 IAR for ARM工程，File-> New-> Workspac创建一个新的工作空间，然后通过Project >Create New Project建立一个ARM的Empty project，点击“OK"后弹出工程保存菜单，填写工程名“STM32uCOSI"，然后点击“保存”，第一个工程建立完毕。步骤二：再建一个工程，通过Project > Create New Project建立一个ARM的Empty project，点击“OK"后弹出工程保存菜单，填写工程名“BOOT"，然后点击“保存”，第二个工程建立完毕。步骤三：建第三个工程，通过Project →> Create New Project建立一个ARM的Empty project，点击“OK"后弹出工程保存菜单，填写工程名“HardWareTest"，然后点击“保存"，第三个工程建立完毕。
上传时间： 2022-06-26
上传用户：
