The Motorola MPC106 PCI bridge/memory controller provides a PowerPCªmicroprocessor common hardware reference platform (CHRPª) compliant bridgebetween the PowerPC microprocessor family and the Peripheral Component Interconnect(PCI) bus. In this document, the term Ô106Õ is used as an abbreviation for the phraseÔMPC106 PCI bridge/memory controllerÕ. This document contains pertinent physicalcharacteristics of the 106. For functional characteristics refer to theMPC106 PCI Bridge/Memory Controller UserÕs Manual.This document contains the following topics:Topic PageSection 1.1, ÒOverviewÓ 2Section 1.2, ÒFeaturesÓ 3Section 1.3, ÒGeneral ParametersÓ 5Section 1.4, ÒElectrical and Thermal CharacteristicsÓ 5Section 1.5, ÒPin AssignmentsÓ 17Section 1.6, ÒPinout Listings 18Section 1.7, ÒPackage DescriptionÓ 22Section 1.8, ÒSystem Design InformationÓ 24Section 1.9, ÒDocument Revision HistoryÓ 29Section 1.10, ÒOrdering InformationÓ 29
上传时间： 2013-11-04
上传用户：as275944189
Internal Interrupts are used to respond to asynchronous requests from a certain part of themicrocontroller that needs to be serviced. Each peripheral in the TriCore as well as theBus Control Unit, the Debug Unit, the Peripheral Control Processor (PCP) and the CPUitself can generate an Interrupt Request.So what is an external Interrupt?An external Interrupt is something alike as the internal Interrupt. The difference is that anexternal Interrupt request is caused by an external event. Normally this would be a pulseon Port0 or Port1, but it can be even a signal from the input buffer of the SSC, indicatingthat a service is requested.The User’s Manual does not explain this aspect in detail so this ApNote will explain themost common form of an external Interrupt request. This ApNote will show that there is aneasy way to react on a pulse on Port0 or Port1 and to create with this impulse an InterruptService Request. Later in the second part of the document, you can find hints on how todebounce impulses to enable the use of a simple switch as the input device.Note: You will find additional information on how to setup the Interrupt System in theApNote “First steps through the TriCore Interrupt System” (AP3222xx)1. It would gobeyond the scope of this document to explain this here, but you will find selfexplanatoryexamples later on.
上传时间： 2013-10-27
上传用户：zhangyigenius
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
CAN与RS232转换节点的设计与实现 介绍将CAN总线接口与RS232总线接口相互转换的设计方法和2种总线电平转换关系，实现CAN总线与各模块的接口设计，制定了相应的软硬件设计方案，并给出软件设计流程图以及部分硬件设计原理图。为CAN总线与RS232总线互联提供了一种方法，对CAN总线与RS232总线接口设备的互联和广泛应用的实现具有重要意义。关键词：CAN总线；RS-232总线；串行通信Design and Realization of CAN and RS232 Transformation NodeZHOU Wei, CHENG Xiao-hong(Information Institute, Wuhan University of Technology, Wuhan 430070)【Abstract】This paper introduces one design method of the CAN bus interface and the RS232 bus interface interconversion, emphasizes two kindof bus level transformation relations, realizes the CAN bus and various modules connection design, formulates the design proposal of correspondingsoftware and hardware, and gives the flow chart of software design as well as the partial schematic diagram of hardware design. It providesonemethod for the CAN bus and the RS232 bus interconnection, has the vital significance to widespread application realization of the CAN busand theRS232 bus interface equipment interconnection.【Key words】CAN bus; RS-232 bus; serial communication
上传时间： 2013-11-04
上传用户：leesuper
MCSÉ-51 Programmer's Guide and Instruction Set The information presented in this chapter is collected from the MCSÉ-51 Architectural Overview and the HardwareDescription of the 8051, 8052 and 80C51 chapters of this book. The material has been selected and rearranged toform a quick and convenient reference for the programmers of the MCS-51. This guide pertains specifically to the8051, 8052 and 80C51.
上传时间： 2013-11-13
上传用户：hj_18
The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
上传时间： 2013-10-22
上传用户：taiyang250072
winCE msdn讲座 XP Embedded Now and the future Windows XP Embedded Developmentand Deployment Model OverviewWindows XP Embedded Component ModelWindows XP Embedded Studio Tools Microsoft WindowsXP Embedded Product Highlights Componentized version of Windows XP Professional~ 12,000 components and updates as of Service Pack 2Flexible localizationSame binaries and API as Windows XP ProfessionalHotfixes and service packsEmbedded Enabling FeaturesRuns on standard PC hardwareSupports boot on hard drives, compact flash, DiskOnChipand read-only mediaSupport for remote install and remote bootHeadless device and remote management supportIntegration with Microsoft management tools
上传时间： 2013-10-31
上传用户：jrsoft
基于变频调速的水平连铸机拉坯辊速度控制系统Frequency Inverter Based Drawing RollerS peedC ontrolSy stem ofHorizontal Continuous Casting MachineA 伟刘冲旅巴(南 华 大 学电气工程学院，衡阳421001)摘要拉坯辊速度控制是水平连铸工艺的关键技术之一，采用变频器实现水平连铸机拉坯辊速度程序控制，由信号发生装置给变频器提供程控信号。现场应用表明该控制系统速度响应快，控制精度高，满足了水平连铸生产的需要。关键词水平连铸拉坯辊速度程序控制变频器Absh'act Speedc ontorlof dr awingor leris on eo fth ek eyte chnologiesfo rho rizontalco ntinuousca stingm achine.Fo rth ispu rpose,fr equencyco nverterisad optedfo rdr awingor lersp eedp rogrammablec ontorlof ho rizontalco ntinuousca stingm achine,th ep rogrammableco ntorlsi gnalto fr equencyc onverteris provided场a signal generator. The results of application show that the response of system is rapid and the control accuracy is high enough to meet thedemand of production of horizontal continuous casting.Keywords Horizontalco ntinuousc asting Drawingor ler Speedp rogrammablec ontrol Ferquencyin verter 随着 现 代 化工业生产对钢材需求量的日益增加，连铸生产能力已经成为衡量一个国家冶金工业发展水平的重要指标之一。近十几年来，水平连铸由于具有投资少、铸坯直、见效快等多方面的优点，国内许多钢铁企业利用水平连铸机来浇铸特种合金钢，发挥了其独特的优势并取得了较好的经济效益〔1,2)0采用 水 平 连铸机浇铸特种合金钢时，由于拉坯机是水平连铸系统中的关键设备之一，拉坯机及其控制性能的好坏直接影响着连铸坯的质量，因此，连铸的拉坯技术便成为整个水平连铸技术的核心。由于钢的冶炼过程是在高温下进行的，钢水温度的变化又容易影响铸坯的质量和成材率，因此，如何能在高温环境下控制好与铸坯速度相关的参数(拉、推程量，中停时间和拉坯频率等)对于确保连铸作业的进一步高效化，延长系统的连续作业时间十分关键。因此，拉坯辊速度控制技术是连铸生产过程控制领域中的关键技术之- [31
上传时间： 2013-10-12
上传用户：gxy670166755
针对使用硬件描述语言进行设计存在的问题，提出一种基于FPGA并采用DSP Builder作为设计工具的数字信号处理器设计方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ设计流程，设计了一个12阶FIR 低通数字滤波器，通过Quartus 时序仿真及嵌入式逻辑分析仪SignalTapⅡ硬件测试对设计进行了验证。结果表明，所设计的FIR 滤波器功能正确，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
上传时间： 2013-11-17
上传用户：lo25643
在综合分析谐波励磁无刷同步发电机励磁控制系统的基础上,对其励磁控制策略进行了研究,开发了一套基于DSP( TMS320F2812) 控制的新型柴油发电机励磁控制系统,该系统采用参数自适应模糊PID 控制励磁,选用交流采样方式实时检测各信号的瞬时特性,系统仿真结果以及在1 台25 kW 工频柴油发电机上的试验结果证明了该控制器具有较好的电压调节特性,系统稳态和暂态性能完全满足发电机对励磁系统的要求。关键词:励磁调节;模糊PID 控制;数字信号处理器;交流采样 Abstract :According to the general analysis of the excitation cont rol system of the harmonious wave excitation brushless synchronous generator and it s characteristics ,a new type of diesel generator excitation cont rol system based on DSP( TMS320F2812) was designed. An adaptive fuzzy PID cont rol of excitation is used in this system. To detect the t ransient characteristics of the signals in a timely manner ,AC sampling was applied.The system simulation result s and the testing result s f rom a 25 kW diesel generator (50 Hz) can prove that the voltage regulation characteristics of the excitation cont rol system are very well ,and both the steadyOstate performance and the t ransient performance of the generator are also good.Key words :excitation cont rol ;fuzzy PID cont rol ;digital signal processor (DSP) ;AC sampling
上传时间： 2013-10-29
上传用户：fxf126@126.com
