源码文件
--show 模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sh…
DSP-CPLD 源代码
汇集 DSP-CPLD 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
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源码文件
library IEEE ; use IEEE.std_logic_1164.all ; use IEEE.std_logic_arith.all ; ENTITY counters IS PORT ( d : IN INTEGER R…
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
LIBRARY IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; ENTITY counter IS P…
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter_1024 is port(clk,clr,en,up…
源码文件
--counter60 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity …
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter_1m is…
源码文件
library IEEE; use IEEE.STD_LOGIC_1164.all; entity TestUSB is end TestUSB; architecture Test of TestUSB is component USB …
源码文件
library IEEE; use IEEE.STD_LOGIC_1164.all; entity CLK is port( clk: in STD_LOGIC; -- 48MHz输入时钟 rst: in STD_LOGIC; …