源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; LIBRARY lpm; USE lp…
DSP-CPLD 源代码
汇集 DSP-CPLD 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
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源码文件
DEPTH = 256; % Memory depth and width are required % WIDTH = 8; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and …
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源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; PACKAGE ram_constant…
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--2选1电路方法1 --library ieee; --use ieee.std_logic_1164.all; --entity mux2_1 is --port(d0,d1,sel:in std_logic; …
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Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg4 IS PORT( d:in std_logic_vector(3 downto 0); ci: IN std_logi…
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library ieee; use ieee.std_logic_1164.all; entity or2a is port ( a: in bit ; b: in bit ; c: out bit); end or2a; architectu…
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/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder4bit is port(cin:in std_logic; …