This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-14
上传用户：fdmpy
飞思卡尔DDR3 PCB布板说明
标签： Layout_Design DDR
上传时间： 2013-11-06
上传用户：dumplin9
宝德“四子星”PR2760T服务器是一款特殊优化设计、性能卓越、安全可靠的高密度机架式服务器产品。完美支持Intel最新5500/5600系列QPI处理器、采用Intel5520芯片组、高速DDR3内存及SATA硬盘热插拔技术，提供超越期待的高性价比。
上传时间： 2013-11-04
上传用户：米卡
白皮书：采用低成本FPGA实现高效的低功耗PCIe接口 了解一个基于DDR3存储器控制器的真实PCI Express® （PCIe®） Gen1x4参考设计演示高效的Cyclone V FPGA怎样降低系统总成本，同时实现性能和功耗目标。点击马上下载！
上传时间： 2013-10-18
上传用户：康郎
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上传时间： 2013-11-23
上传用户：shen_dafa
关于DDR，DDR2,DDR3和MMC的标准规范。
标签： DDR
上传时间： 2013-11-30
上传用户：thesk123
JESD79-3C_DDR3 SDRAM，DDR3最新规范
上传时间： 2021-11-29
上传用户：aben
HI3520DV400全套资料（Cadence arregro原理图+PCB+bom+镜像软件），1个HDMI输入，1个HDMI输出，1个3.5音频输入，1个3.5音频输出。2GB-DDR3，2个USB2.0,1个LAN，已经调试通过，固件都已经打包好。拿来就可以打板生产，包括原理图，PCB，u-boot,kernel,rootfs。
标签： hi3520dv400 cadence arregro
上传时间： 2021-12-28
上传用户：
核心板说明（1）DDR模板：RK3288-LPDDR3P232SD6-V12-20140623HXS（2）适用的平台：RK3288；（3）支持的DDR类型：LPDDR3_2PCS*32BIT（4）最大支持容量：4G（2PCS*32BIT）；（5）板层：6 Layer；（6）贴片方式：DDR器件单面贴,其它器件双面贴；（7）面积：35mm*35mm；
上传时间： 2022-02-02
上传用户：
10个Altium Designer经典案例，含原理图+PCB8层板设计 飞思卡尔IMX6 4片DDR3 设计 DSN原理图+PCB；6层板设计 全志H8 VR一体机设计 DSN原理图+PCB；6层板设计 LPC32X0核心板 SCH+PCB2层板设计 AT89C52 + RC500 Mifare 读卡器PCB 和原理图；2层板设计 16进11出PLC设计资料，含原理图、PCB、物料单、供应商、物料价格；2层板设计 显示屏板SCH+PCB文件；
标签： Altium Designer AD案例
上传时间： 2022-04-09
上传用户：jiabin
