XAPP806 -决定DDR反馈时钟的最佳DCM相移
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Doub...
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This application note describes how to build a system that can be used for determining theoptimal phase shift for a Doub...
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a hig...
厂商把产品命名为DDR3-1600,则意味着该厂商将规定该SDRAM器件的峰值传输速率定为1,600MT/s。虽然这些器件确实能够达到所规定的传输速率,但在实际工作负载情况下却不能持续保持该速率。原因在于行地址冲突、数据总线转换损耗、写...
DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M
This open source, event-drived, RAM constrained embedded system.
AT89C52扩展外部双口RAM(IDT7132),在Keil C51环境下测试,和一般的RAM使用方法相当!用串口调试助手观看测试结果