XAPP806 -决定DDR反馈时钟的最佳DCM相移
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Doub...
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This application note describes how to build a system that can be used for determining theoptimal phase shift for a Doub...
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a hig...
DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M
Stellaris(群星)单片机加上32KB串行SRAM(英) INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO ...
一个比较有参考价值的sram IP核,对SOPC感兴趣的人士有一定的指导意义!该程序是采用avalon总线,可以直接内嵌进SOPC Builder。