This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone.
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently suppor...
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This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently suppor...
Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.
SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口,方便与其他IP连接使用。
load flow algorithm, with entering bus data and line data it solves the load flow with newton method.
This program is a series of 51 single-chip microcomputer simulation IIC bus, the memory of the 24 operations