前言智能仪表课采用了《单片机原理与接口技术》作为教材，这是一门实践性极强的课程，理论和实验教学的有机结合，是提高教学质量的唯一途径。为密切配合理论教学，针对SICElab赛思开放式综合实验/仿真系统，我们编写了配套的实验教材。SICElab赛思开放式综合实验/仿真系统采用了符合单片机开发过程的“仿真式”组合设计思想，使得所有的实验模块及CPU资源均全力对用户开放，从而充分满足“验证式”→“模仿式”→“探索式”→“开发式”的由浅入深的各种实验要求。赛思开放式综合实验/仿真系统采用伟福G6W仿真器,为用户提供了一个大集成软件环境，统一的界面，包含一个项目管理器，一个功能强大的编辑器，汇编Make、Build和调试工具并提供一个与第三方编译器的接口，具有DOS/WINDOWS双平台,仿真器与实验平台分离，采用“仿真”方式进行实验，同时，允许进行脱机运行工作，所以，实验过程是与实际开发过程完全一致的。仿真器使用的是双“CPU”架构方式，100%资源出让，100%实时，100%无条件硬件断点，可满足学生实验，毕业设计，参加电子竞争，教师科研所需。第一章简单介绍了赛思开放式综合实验/仿真系统的组成（包括实验平台、仿真器、软件支持、开关电源），实验内容，实验方式，支持器件等。第二章选编了二十例验证式实验，包括实验平台操作，连接仿真器、PC机，利用DOS和WINDOWS平台软硬件结合的实验，按由浅入深原则排列。第三章选编了十六例模仿和探索开发式实验。教师和学生可根据课时和具体情况选择实验内容，或自行设计新的实验内容。由于课时所限，有的实验可让学生在课后开放实验室时完成，以提高学生动手能力，提高教学质量，培养学生创新精神。附录一介绍了综合实验平台各模块的电路图，附录二是实验平台键盘操作仿真方法说明。由于时间匆忙，加上编者水平有限，难免有错漏之处，请读者不吝赐教。
上传时间： 2013-10-22
上传用户：sunshie
汇编器在微处理器的验证和应用中举足轻重，如何设计通用的汇编器一直是研究的热点之一。本文提出了一种开放式的汇编器系统设计思想，在汇编语言与机器语言间插入中间代码CMDL（code mapping description language）语言，打破汇编语言与机器语言的直接映射关系，由此建立起一套描述汇编语言与机器语言的开放式映射体系。基于此开放式映射体系开发了一套汇编器系统，具有较高层次上的通用性和可移植性。【关键词】指令集，CMDL，汇编器，开放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to Build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【关键词】instruction set, symbol table, assembler, lexical analysis, retargetability
上传时间： 2013-10-10
上传用户：meiguiweishi
1 /**————————————————————2 〖说明〗I2C总线驱动程序(用两个普通IO模拟I2C总线)3 包括100Khz(T=10us)的标准模式(慢速模式)选择，4 和400Khz(T=2.5us)的快速模式选择，5 默认11.0592Mhz的晶振。6 〖文件〗PCF8563T.C ﹫2001/11/2 77 〖作者〗龙啸九天 c51@yeah.net http://www.c51bbs.co /8 〖修改〗修改建议请到论坛公布 http://www.c51bbs.co m9 〖版本〗V1.00A Build 080310 —————————————————————*/1112 #ifndef SDA13 #define SDA P0_014 #define SCL P0_115 #endif1617 extern uchar SystemError;1819 #define uchar unsigned char20 #define uint unsigned int21 #define Byte unsigned char22 #define Word unsigned int23 #define bool bit24 #define true 125 #define false 02627 #define SomeNOP(); _nop_();_nop_();_nop_();_nop_();2829 /**--------------------------------------------------------------------------------30 调用方式：void I2CStart(void) ﹫2001/07/0 431 函数说明：私有函数，I2C专用32 ---------------------------------------------------------------------------------*/33 void I2CStart(void)34 {35 EA=0;36 SDA=1; SCL=1; SomeNOP();//INI37 SDA=0; SomeNOP(); //START38 SCL=0;39 }4041 /**--------------------------------------------------------------------------------42 调用方式：void I2CStop(void) ﹫2001/07/0 443 函数说明：私有函数，I2C专用44 ---------------------------------------------------------------------------------*/45 void I2CStop(void)46 {47 SCL=0; SDA=0; SomeNOP(); //INI48 SCL=1; SomeNOP(); SDA=1; //STOP49 EA=1;50 }5152 /**--------------------------------------------------------------------------------53 调用方式：bit I2CAck(void) ﹫2001/07/0 454 函数说明：私有函数，I2C专用，等待从器件接收方的应答55 ---------------------------------------------------------------------------------*/56 bool WaitAck(void)57 {58 uchar errtime=255;//因故障接收方无ACK，超时值为255。59 SDA=1;SomeNOP();60 SCL=1;SomeNOP();61 while(SDA) {errtime--; if (!errtime) {I2CStop();SystemError=0x11;return false;}}62 SCL=0;63 return true;
上传时间： 2014-04-11
上传用户：xg262122
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to Build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
This application note describes how to Build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上传时间： 2013-10-15
上传用户：euroford
This application note describes a reference system which illustrates how to Build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note describes how to set up thespecific clocking structure required for the SerDes interface and the constraints to be added tothe UCF file. This reference system is complete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.
上传时间： 2013-11-01
上传用户：truth12
A Computer-On-Module, or COM, is a Module with all components necessary for a bootable host computer, packaged as a super component. A COM requires a Carrier Board to bring out I/O and to power up. COMs are used to Build single board computer solutions and offer OEMs fast time-to-market with reduced development cost. Like integrated circuits, they provide OEMs with significant freedom in meeting form-fit-function requirements. For all these reasons the COM methodology has gained much popularity with OEMs in the embedded industry. COM Express® is an open industry standard for Computer-On-Modules. It is designed to be future proof and to provide a smooth transition path from legacy parallel interfaces to LVDS (Low Voltage Differential Signaling) interfaces. These include the PCI bus and parallel ATA on the one hand and PCI Express and Serial ATA on the other hand.
上传时间： 2013-11-05
上传用户：Wwill
Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous ways to Build a 1-Wire master (see reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications"). Thisdocument describes the DS1WM, a synthesizable 1-Wire master that can be implemented in an application-specificintegrated circuit (ASIC) or field-programmable gate array (FPGA).
上传时间： 2014-12-22
上传用户：xanxuan
Abstract: This application note describes how to create, Build, and debug applications targeted for the MAXQ1050 RISC
标签： MAXQ CrossStudio 1050 30
上传时间： 2014-08-11
上传用户：qwerasdf
The use of the Wind River VxWorks Real-Time Operating System (RTOS) on Virtex™-4embedded PowerPC™ processors continues to be a popular choice for high performanceFPGA designs. The introduction of the Wind River Workbench design environment has enableda new and easier way for designers to control the configuration of the VxWorks kernel. Thisguide shows the steps required to Build and configure a ML403 Embedded DevelopmentPlatform to boot and run the VxWorks RTOS. A VxWorks bootloader is created, programmedinto Flash, and used to boot the design. The concepts presented here can be scaled to anyPowerPC enabled development platform.
上传时间： 2013-10-26
上传用户：agent
