Boundary
共 83 篇文章
Boundary 相关的电子技术资料，包括技术文档、应用笔记、电路设计、代码示例等，共 83 篇文章，持续更新中。
ARMJTAG调试原理
介绍ARM JTAG调试的基本原理。基本的内容包括了TAP (TEST ACCESS PORT) 和BOUNDARY-SCAN ARCHITECTURE的介绍，在此基础上，结合ARM7TDMI详细介绍了的JTAG调试原理。
04 calgary PhD Numerical Solutions to Altimetry-Gravimetry Boundary Value Problems in Coastal Region
资料->【E】光盘论文->【E1】斯坦福博士论文->04 calgary PhD Numerical Solutions to Altimetry-Gravimetry Boundary Value Problems in Coastal Regions.pdf
BSDJTAG
Boundary Scan File FormatsBoundary Scan File FormatsBoundary Scan File FormatsBoundary Scan File FormatsBoundary Scan File Formats
期刊论文：Stereo Matching on Objects with Fractional Boundary [cvpr07]
·Stereo Matching on Objects with Fractional Boundary [cvpr07]
使用XC9500 JTAG边界扫描接口
IEEE Boundary-Scan Standard 1149.1, also known as<BR>JTAG, is a testing standard that uses software
在边界扫描系统中运用在系统编程
The XC9500 family performs both in-system programming and IEEE 1149.1 boundary-scan (JTAG) testing v
使用XC9500 JTAG边界扫描接口
IEEE Boundary-Scan Standard 1149.1, also known as<BR>JTAG, is a testing standard that uses software
一种单片机的在线编程测试方法研究
<p>单片机是一种集成电路芯片,在工业控制领域得到广泛的应用。而传统的单片机测试方法是先编程后上测试机测试,依赖下载器和人工操作,导致生产效率偏低。该文研究了基于ATE测试系统的单片机在线编程测试方法。以C8051F061型单片机电路为例,利用JTAG边界扫描原理设计了基于J750EX测试系统的单片机的在线测试方案,实现了J750EX测试系统对单片机的在线编程测试。实验结果表明,一种单片机的在线编
83390067ARMJTAG.rar
这篇文章主要介绍ARM JTAG调试的基本原理。基本的内容包括了TAP (TEST ACCESS PORT) 和BOUNDARY-SCAN ARCHITECTURE的介绍，在此基础上，结合ARM7TDMI详细介绍了的JTAG调试原理
Boundary-Scan Tutorial
Boundary-Scan Tutorial
JTAG基础知识
<p>IEEE1149.1的产生</p><p>1985年由IBM、AT&T、Texas Instruments、Philips Electronics NV、Siemens、Alcatel和Ericsson等公司成立的JETAG</p><p>（Joint European Test Action Group）提出了边界扫描技术。1986年由于其它地区的一些公司的加入，JETAG改名为JTA
应用ANSOFT-HFSS对曲面结构贴片天线的模拟
<p>结构体的具体尺寸如下所示：a=1.20<br/>h=0.620其中介质锥的介电常数E=2.0。选定工作频率为f=15GHz相对应的真空中的波长为0=20<br/>mm，这样结构体的儿何尺寸己经完全确定，下面介绍求解的全过程选定求解方式为（Solution Type）Driven modal<br/>1.建立所求结构体的几何模型（单位：mm）。<br/>由于此结构体的几何形状较简单，使用工具栏
50W隔离型离线式DC.pdf
<p>ABSTRACT</p><p>The flyback power stage is a popular choice for single and multiple output dc-to-dc converters at power</p><p>levels of 150 Watts or less. Without the output inductor required in buc
CPU可测试性设计
<p><span style="font-size: 9pt; font-family: 宋体;">可测试性设计（Design-For-Testability，DFT）已经成为芯片设计中不可或缺的重要组成部分。它通过在</span></p><p><span style="font-size: 9pt; font-family: 宋体;">芯片的逻辑设计中加入测试逻辑提高芯片的可测试性。在高性能通用
2民生行用卡源代码
Received: from mail.creditcard.cmbc.com.cn (unknown [111.205.122.39])<br />
by newmx82.qq.com (NewMx) with SMTP id <br />
for <714620454@QQ.COM>; Fri, 20 Oct 2017 03:56:09 +0800<br />
X-QQ-
The decision of a boundary problem for the equation of Puassona Method of splittings usual and повы
The decision of a boundary problem for the equation of Puassona
Method of splittings usual and повышеной accuracy
The decision of a boundary problem for the differential equation of elliptic type of the second orde
The decision of a boundary problem for the differential equation of elliptic type of the second order a splitting method
The decision of a boundary problem a method of Galerkin
The decision of a boundary problem a method of Galerkin
This program incorporates the FV method for solving the Navier-Stokes equations using 2D, Cartesian
This program incorporates the FV method for solving the Navier-Stokes equations using 2D, Cartesian grids and the staggered arrangement of variables. Variables are stored as 2D arrays. SIMPLE method i