CH341系列编程器芯片usb转串口Altium Designer AD原理图库元件库CSV text has been written to file : 1.9 - CH341系列编程器芯片.csvLibrary Component Count : 56Name Description----------------------------------------------------------------------------------------------------CH311Q PC debug port monitorCH331T Mini USB Disk ControllerCH340G CH340H USB to TTL Serial / UART, USB to IrDACH340T USB to TTL Serial / UART, USB to IrDACH340R USB to IrDA, USB to RS232 SerialCH340S_P USB to Print Port / ParallelCH340S_S USB to TTL Serial / UART, pin compatible with CH341CH341A_S USB to TTL Serial / UART / I2C/IICCH341S_P USB to Print Port / ParallelCH341A_P USB to Print Port / ParallelCH341S_S USB to TTL Serial / UARTCH341S_X USB to EPP Parallel / SPI / I2C/IICCH341A_X USB to EPP Parallel / SPI / I2C/IICCH341T USB to TTL Serial / UART / I2C/IICCH345T USB to MidiCH352L_M PCI to 8255 mode 2 Parallel for MCU and 16C550 UART / IrDACH352L_P PCI to Print Port / Parallel and 16C550 UART / IrDACH352L_S PCI to Dual 16C550 UART, TTL Serial*2 / IrDA*1CH362L PCI Device / Slave only for RAM / Expansion ROMCH364F Member of CH364 chipsetsCH364P PCI Device / Slave Embedded Flash ROM, for Expansion ROMCH365P PCI Device / Slave, for I/O port or RAM / ROMCH372T USB Device / Slave for MCU, ParallelCH372A USB Device / Slave for MCU, ParallelCH372V USB Device / Slave for MCU, ParallelCH374S USB Host & Device / Slave for MCU, parallel / SPICH374T USB Host & Device / Slave for MCU, parallel / SPICH375S USB Host & Device / Slave for MCU, parallel / UART SerialCH375A USB Host & Device / Slave for MCU, parallel / UART SerialCH375V USB Host & Device / Slave for MCU, parallel / UART SerialCH411G FDC MFM encode and decodeCH421A Dual port bufferCH421S Dual port bufferCH423D I2C/IIC I/O expander, 16 GPO + 8 GPIO, 128 LEDs DriveCH423S I2C/IIC I/O expander, 16 GPO + 8 GPIO, 128 LEDs DriveCH423D_D I2C/IIC I/O expander, 16 GPO + 8 GPIO, 128 LEDs DriveCH423S_D I2C/IIC I/O expander, 16 GPO + 8 GPIO, 128 LEDs DriveCH423G I2C/IIC I/O expander, 6 GPO + 5 GPIOCH432Q Dual 16C550 UART with IrDA, parallel / SPICH432T SPI Dual 16C550 UART with IrDACH450K 6 Digits / 48 LEDs Drive & 8x6 Keyboard, I2C/IICCH450H 6 Digits / 48 LEDs Drive & 8x6 Keyboard, I2C/IICCH450L 8 Digits / 64 LEDs Drive & 8x8 Keyboard, I2C/IICCH451L 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH451S 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH451D 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH452L_2 8 Digits / 64 LEDs Drive & 8x8 Keyboard, I2C/IICCH452L_4 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH452S_2 8 Digits / 64 LEDs Drive & 8x8 Keyboard, I2C/IICCH452S_4 8 Digits / 64 LEDs Drive & 8x8 Keyboard, 4 Wire Interface, SPICH453S 16 Digits / 128 LEDs Drive, I2C/IICCH453D 16 Digits / 128 LEDs Drive, I2C/IICPCI 32Bit PCI Bus, simple / short cardPCI32 32Bit PCI BusUSB USB Port
标签： ch341 编程芯片 usb 串口 altium designer
上传时间： 2022-03-13
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电子书-RTL Design Style Guide for Verilog HDL540页A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
标签： RTL verilog hdl
上传时间： 2022-03-21
上传用户：canderile
针对嵌入式产品程序更新问题,提出了一种基于IAP技术的STM32单片机在线固件升级方案,设计了STM32单片机最小系统硬件电路和USB转串口通信电路,并给出了Bootloader程序、APP程序、PC上机程序的实现流程.实验结果表明,该方案具有简单实用、稳定性高、维护成本低和设备使用效率高的特点,适用于嵌入式产品升级.For the problem of updating embedded products program,an online firmware upgrade scheme of STM32 single chip microcomputer based on IAP technology is proposed.This scheme not only elaborates the principle of IAP technology in detail but also provides the design of the minimum system hardware circuit of STM32 MCU,the design of USB for serial communication circuit,and the implementation flow of Bootloader program,APP program and PC program.The experiment results show that the scheme is simple,practical and highly stable.In addition,it can be used to actual embedded product upgrading,significantly reducing maintenance costs and improving the efficiency of equipment.
上传时间： 2022-03-25
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This manual documents the Microcontroller profile of version 7 of the ARM® Architecture, the ARMv7-M architecture profile. For short definitions of all the ARMv7 profiles see About the ARMv7 architecture, and architecture profiles on page A1-20.ARMv7 is documented as a set of architecture profiles. The profiles are defined as follows: ARMv7-A The application profile for systems supporting the ARM and Thumb instruction sets, and requiring virtual address support in the memory management model. ARMv7-R The realtime profile for systems supporting the ARM and Thumb instruction sets, and requiring physical address only support in the memory management model ARMv7-M The microcontroller profile for systems supporting only the Thumb instruction set, and where overall size and deterministic operation for an implementation are more important than absolute performance. While profiles were formally introduced with the ARMv7 development, the A-profile and R-profile have implicitly existed in earlier versions, associated with the Virtual Memory System Architecture (VMSA) and Protected Memory System Architecture (PMSA) respectively.
标签： arm
上传时间： 2022-06-02
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Spartane-6 LXand LXT FPGAs are available in various speed grades, with -3 having the highest performance. The DC and AC electrical parameters of the Automotive XA Spartan-6 FPGAs and Defense-grade Spartan-6Q FPGAs devices are equivalent to the commercial specifications except where noted. The timing characteristics of the commercial(XC)-2 speed grade industrial device are the same as for a-2 speed grade commercial device. The -2Q and -3Q speed grades are exclusively for the expanded(Q) temperature range. The timing characteristics are equivalent to those shown for the-2 and-3speed grades for the Automotive and Defense-grade devices.Spartan-6 FPGA DC and AC characteristics are specified for commercial (C), industrial (), and expanded (Q) temperature ranges. Only selected speed grades and/or devices might be available in the industrial or expanded temperature ranges for Automotive and Defense-grade devices.
上传时间： 2022-06-19
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German universities and scientists have repeatedly set the intermational standard in drive technology. Identification and active compensation of natural frequencies in oscillatory mechanics, status controls with monitoring structures incorporating acceleration sensors, adaptive compensation of measurement system deficiencies, self-adjusting detent torque compensation… everything invented with only a single aim in mind: to continue improv-ing the motion control, dynamics, precision and processing speed of your machines. For the industrial applicabability of this technology scientific publications in proceedings and laboratory test rigs are not enough. These features consequenty need to be converted into cost-efficient and easily manageable products. That 's exactly what we have done.So in future, if you should need more than today ' smarket can offer you, now everything isgoing to be alright. With our new high-performance ServoOne drive series you will experi-ence
标签： servoone
上传时间： 2022-06-24
上传用户：kingwide
Note: Before commissioning the value of the connected mains voltage must be set in the servo controller(factory setting=3×400 V AC). More detailed information see chapter 4"Commissioning".通讯接口所有的Servo-One系列均有USB及TCP/IP通讯接口，可通过LT-I公司的Drive-Manager5软件进行通讯，进行相关参数的读写和现场调试，详情请参考章节.…软件调试。Servo-One Junior:X9（USB1.1）TCP/IP（开发中）Servo-One:X2（USB1.1）X3（TCP/IP）Note: The faults can be acknowledged in accordance with their programmed reaction(ER) or reset via a 24 V-reset(X9/10)(ER.).Attention: Faults marked with a dot can only be reset, after the cause of the fault has been eliminated.显示为当前版本V5.4.0同时，相应的USB接口驱动也在对应的安装文件夹内，例：C:\Program FileLTI DRiVES GmbHILTi DriveManager 5.4.0drivers
标签： servoone
上传时间： 2022-06-24
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1.特色（CY7C68013A/14A/15A/16A）■USB 2.0USB IF 高速性能且经过认证（TID#40460272）■单芯片集成USB2.0收发器、智能串行接口引擎（SIE）和增强型8051微处理器■适用性、外观和功能均与FX2兼容a引脚兼容口目标代码兼容a功能兼容（FX2LP是超集）■超低功耗：lcc在任何模式下都不超过85mA a适合总线和电池供电的应用软件：8051代码运行介质：3内部RAM，通过USB下载口内部RAM，从EEPROM加载口外部存储设备（128引脚封装）■16K字节片上代码/数据RAM■四个可编程的BULK/INTERRUPT/ISOCHRONOUS 端点口缓冲区大小选项：两倍，三倍，四倍■附加的可编程（BULK/INTERRUPT）64位端点■8位或16位外部数据接口■可生成智能介质标准错误校正码ECC
标签： usb
上传时间： 2022-06-25
上传用户：zhaiyawei
摘要：本系统以ICL8038集成块为核心器件，制作一种函数信号发生器，制作成本较低。适合学生学习电子技术测量使用。ICL8038是一种具有多种波形输出的精密振荡集成电路，只需要个别的外部元件就能产生从0.001Hz~30KlHz的低失真正弦波、三角波、矩形波等脉冲信号。输出波形的频率和占空比还可以由电流或电阻控制。另外由于该芯片具有调制信号输入端，所以可以用来对低频信号进行频率调制。关键词：函数信号发生器频率调制Abstract：The system ICL8038 integrated block as the core device，producing a kind of function signal generator，producing low cost.Suitable for students to learn the use of electronic technology measurement.ICL8038 is a kind of multi-precision oscillator waveform output integrated circuits，a separate external components only need to be able to generate from the 0.001Hz ~30KHz low-distortion sine wave，triangle wave，square wave pulse signal，etc..Output waveform of the frequency and duty cycle can also be controlled by a currentor resistance.In addition，as the chip has a modulated signal input terminal，it can be used to low-frequency signal is frequency modulation.
上传时间： 2022-07-04
上传用户：zhanglei193
PrefaceDuring the past years, there has been a quickly rising interest in radio access technologies for providingmobile as well as nomadic and fixed services for voice, video, and data. The difference indesign, implementation, and use between telecom and datacom technologies is also becoming moreblurred. One example is cellular technologies from the telecom world being used for broadband dataand wireless LAN from the datacom world being used for voice-over IP.Today, the most widespread radio access technology for mobile communication is digital cellular,with the number of users passing 5 billion by 2010, which is more than half of the world’s population.It has emerged from early deployments of an expensive voice service for a few car-borne users,to today’s widespread use of mobile-communication devices that provide a range of mobile servicesand often include camera, MP3 player, and PDA functions. With this widespread use and increasinginterest in mobile communication, a continuing evolution ahead is foreseen.This book describes LTE, developed in 3GPP (Third Generation Partnership Project) and providingtrue 4G broadband mobile access, starting from the first version in release 8 and through the continuingevolution to release 10, the latest version of LTE. Release 10, also known as LTE-Advanced,is of particular interest as it is the major technology approved by the ITU as fulfilling the IMTAdvancedrequirements. The description in this book is based on LTE release 10 and thus provides acomplete description of the LTE-Advanced radio access from the bottom up.Chapter 1 gives the background to LTE and its evolution, looking also at the different standardsbodies and organizations involved in the process of defining 4G. It also gives a discussion of the reasonsand driving forces behind the evolution.Chapters 2–6 provide a deeper insight into some of the technologies that are part of LTE and itsevolution. Because of its generic nature, these chapters can be used as a background not only for LTEas described in this book, but also for readers who want to understand the technology behind othersystems, such as WCDMA/HSPA, WiMAX, and CDMA2000.Chapters 7–17 constitute the main part of the book. As a start, an introductory technical overviewof LTE is given, where the most important technology components are introduced based onthe generic technologies described in previous chapters. The following chapters provide a detaileddescription of the protocol structure, the downlink and uplink transmission schemes, and the associatedmechanisms for scheduling, retransmission and interference handling. Broadcast operation andrelaying are also described. This is followed by a discussion of the spectrum flexibility and the associated
上传时间： 2022-07-08
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