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BIt

  • Avalon_VGA

    Avalon_VGA,-- This design provides an interface to the Alcahest VGA daughter card. -- The design comprises of an 8-BIt VGA driver with Avalon bus interfaces. There are a total of -- three Avalon interfaces.

    标签: Avalon_VGA

    上传时间: 2015-07-07

    上传用户:kikye

  • Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL c

    Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/BIt accurate model * Synthesizable VHDL model

    标签: Algorithm Decoder DVB-RCS Release

    上传时间: 2015-07-10

    上传用户:清风冷雨

  • 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in

    关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-BIt floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 BIt integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.

    标签: investigates implementing pipelines circuits

    上传时间: 2015-07-26

    上传用户:CHINA526

  • The objective of this projectis to design, model and simulate an autocorrelation generator circuit

    The objective of this projectis to design, model and simulate an autocorrelation generator circuit using 4-BIt LFSR. the register and LFSR will used D flip-flop and some gates. By the autocorrelation concept, there should be 2 same length vectors, for calculating the autocorrelation , we have to design the register for storing the original vector and the shifter for make time delay.

    标签: autocorrelation objective generator projectis

    上传时间: 2015-08-17

    上传用户:ikemada

  • 逻辑分析仪 PC发送到单片机的命令共7个字节: 第一字节是触发信号

    逻辑分析仪 PC发送到单片机的命令共7个字节: 第一字节是触发信号,每BIt对应一路信号,1为高电平触发,0为低电平触发; 第二字节是触发有效信号,每BIt对应一路信号,1为忽略,0为有效; 第三、四字节是采样时间,对应如下: 2us=0x0402,5us=0x0a02,10us=0x1402,10us=0x2802,50us=0x6402,100us=0xc802,200us=0x3203,500us=0x7d03,1ms=0xfa03,2ms=0x7d04,4ms=0xfa04,8ms=0x7d05,16ms=0xfa05; 第五、六字节是一样的,为预触发:8=0%,7=12.5%,6=25%,5=37.5%,4=50%,3=62.5%,2=75%,1=87.5% 第七字节为模式,0=普通模式;1=外部时钟,上升延;2=外部时钟,下降延;3=外部触发,上升延;4=外部触发,下降延;5=静态模式;6没有查到,不知道是什么;7为测试模式的二进制信号;8为测试模式的AA、55;9为测试模式的清零。

    标签: 字节 逻辑分析仪 发送 单片机

    上传时间: 2013-12-12

    上传用户:luke5347

  • Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols.

    Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 BIt. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register.

    标签: symbols length Hard-decision Codeword

    上传时间: 2014-07-08

    上传用户:曹云鹏

  • 由delphi实现的bt下载器示例程序

    由delphi实现的bt下载器示例程序,带全部源码和BT协议 包中文件说明: BTDemo.dpr, BTDemoF.pas, BTDemoF.dfm -- 一个简单的bt下载器,支持多个.torrent文件同时下载 btutils.pas -- 核心bt组件 DCP*.pas -- SHA算法源码(复制自DEC组件包) InetUtils.pas -- 提供Internet下载的函数库 SimpleSocks.pas -- socket组件(TCP) SortLists.pas -- 排序的List组件 ThreadTimer.pas -- 定时器与线程池 DelayLists.pas -- 一个延时5秒再释放Object的队列 FastShareMem.pas, MemPools.pas, ShareGlobals.inc -- 由ThreadTimer内部使用 BIt Torrent Specification.htm -- BT协议文档

    标签: delphi 下载器 程序

    上传时间: 2015-09-10

    上传用户:lizhen9880

  • /*** *** *** *** *** *** *** *** *** *** *** *** **/ //**此映射表用来映射LED模块不译码时

    /*** *** *** *** *** *** *** *** *** *** *** *** **/ //**此映射表用来映射LED模块不译码时,显示的字符和必须输入的数据的关系 //**每段和对应比特位的关系见示意图 // g // --- --- // b | a |f | | <---显示0时点亮的段为gfedcb // --- // c | |e | | 那么写入数据为0x7e // --- --- // d // BIt: 7 6 5 4 3 2 1 0 // 段位: g f e d c b a

    标签: LED 映射 模块 译码

    上传时间: 2013-11-25

    上传用户:

  • the c languge is used for the GPS field.The pogram is the PARITY CHECK ,which is one kind data of th

    the c languge is used for the GPS field.The pogram is the PARITY CHECK ,which is one kind data of the GPS data .and it is used for correcting one BIt error

    标签: the is languge PARITY

    上传时间: 2013-11-26

    上传用户:xiaodu1124

  • sd2003芯片资料及源码

    sd2003芯片资料及源码,C51下的,可以直接使用,不是厂方提供的测试程序, 相应子程序: extern void ini_SD2003(void) extern BIt mend_scl_SD2003(void) extern BIt start_BIt_SD2003(void) extern void stop_BIt_SD2003(void) extern void ack_SD2003(void) extern void no_ack_SD2003(void) extern void mast_ack_SD2003(void) extern void write_8BIt_SD2003(UCHAR ch) extern UCHAR Read_8BIt_SD2003(void) extern void write_8BIt_SD2003_R(UCHAR ch) extern UCHAR Read_8BIt_SD2003_R(void) extern BIt Readblock_SD2003(UCHAR ucommand,UCHAR *p) extern BIt Writeblock_SD2003(UCHAR ucommand,UCHAR *p)

    标签: 2003 sd 芯片资料 源码

    上传时间: 2015-09-14

    上传用户:zl5712176