-- Simple Robot Control Program -------------------------------------------------------------------------- -- Left is left IR sensor - 1=object to left -- Right is rigth IR sensor - 1=object to right -- Lmotor_dir 1=forward 0=reverse -- Rmotor_dir 1=forward 0=reverse -- Lmotor_speed 111=fast 000=slow -- Rmotor_speed 111=fast 000=slow
标签： Control Program Simple Robot
上传时间： 2013-11-27
上传用户：风之骄子
无线传感器网络，粒子滤波，particle filter for sensor network
标签： 无线传感器网络
上传时间： 2016-11-14
上传用户：firstbyte
The TMS320C54x, TMS320LC54x, and TMS320VC54x fixed-point, digital signal processor (DSP) families (hereafter referred to as the ’54x unless otherwise specified) are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors also provide an arithmetic logic unit (ALU) that has a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. These DSP families also provide a highly specialized instruction set, which is the basis of the operational flexibility and speed of these DSPs.
标签： TMS 320 fixed-point processor
上传时间： 2013-12-27
上传用户：宋桃子
FatFs06.rar FatFs is a generic file system module to implement the FAT file system to small embedded systems. The FatFs is written in compliance with ANSI C, therefore it is independent of hardware architecture. It can be incorporated into cheap microcontrollers, such as 8051, PIC, AVR, SH, Z80, H8, ARM and etc..., without any change.
标签： system FatFs file implement
上传时间： 2016-11-17
上传用户：chenxichenyue
The System Management BIOS Reference Specification addresses how motherboard and system vendors present management information about their products in a standard format by extending the BIOS interface on Intel architecture systems. The information is intended to allow generic instrumentation to deliver this data to management applications that use CIM (the WBEM data model) or direct access and eliminates the need for error prone operations like probing system hardware for presence detection.
标签： Specification motherboard Management Reference
上传时间： 2013-12-10
上传用户：凤临西北
DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上传时间： 2014-11-01
上传用户：l254587896
Batch version of the back-propagation algorithm. ％ Given a set of corresponding input-output pairs and an initial network ％ [W1,W2,critvec,iter]=batbp(NetDef,W1,W2,PHI,Y,trparms) trains the ％ network with backpropagation. ％ ％ The activation functions must be either linear or tanh. The network ％ architecture is defined by the matrix NetDef consisting of two ％ rows. The first row specifies the hidden layer while the second ％ specifies the output layer. ％
标签： back-propagation corresponding input-output algorithm
上传时间： 2016-12-27
上传用户：exxxds
％ Train a two layer neural network with the Levenberg-Marquardt ％ method. ％ ％ If desired, it is possible to use regularization by ％ weight decay. Also pruned (ie. not fully connected) networks can ％ be trained. ％ ％ Given a set of corresponding input-output pairs and an initial ％ network, ％ [W1,W2,critvec,iteration,lambda]=marq(NetDef,W1,W2,PHI,Y,trparms) ％ trains the network with the Levenberg-Marquardt method. ％ ％ The activation functions can be either linear or tanh. The ％ network architecture is defined by the matrix NetDef which ％ has two rows. The first row specifies the hidden layer and the ％ second row specifies the output layer.
标签： Levenberg-Marquardt desired network neural
上传时间： 2016-12-27
上传用户：jcljkh
Train a two layer neural network with a recursive prediction error ％ algorithm ("recursive Gauss-Newton"). Also pruned (i.e., not fully ％ connected) networks can be trained. ％ ％ The activation functions can either be linear or tanh. The network ％ architecture is defined by the matrix NetDef , which has of two ％ rows. The first row specifies the hidden layer while the second ％ specifies the output layer.
标签： recursive prediction algorithm Gauss-Ne
上传时间： 2016-12-27
上传用户：ljt101007
电信运营商收入保障系统设计与实现 本文研究领域涉及嵌入式系统开发流程和方法、嵌入式移动通信终端系统软硬件框架、NOR Flash芯片体系结构、Flash芯片驱动软件的自适应算法、Flash映像文件空间压缩算法、霍尔传感器(Hall Sensor）驱动软件原理和实现、LCD驱动软件设计、LCD颜色校正算法和实现、LCD抗静电硬件保护与软件恢复序列的实现。
上传时间： 2013-12-13
上传用户：mikesering
