多功能高集成外围器件6. 1 多功能高集成外围器件82371PCI的英文名称：Peripheral Component Interconnect （外围部件互联PCI总线）；82371是PCI总线组件。ISA是：Industry Standard Architecture（工业标准体系结构）IDE是 （Integrated Device Electronics）集成电路设备简称PIIX4PIIX4器件（芯片）的特点1、是一种支持Pentium和PentiumII微处理器的部件。2、82371对ISA桥来说，是一种多功能PCI总线。3、对可移动性和桌面深绿色环境均提供支持。4、电源管理逻辑。5、被集成化的IDE控制器。6、增强了性能的DMA控制器。 （7）基于两个82C59的中断控制器。（8）基于82C54芯片的定时器。（9）USB（Universal Serial Bus）通用串行总线。（10）SMBus系统管理总线。（11）实时时钟（12）顺应Microsoft Win95所需的功能其芯片的逻辑框图如图6-1所示。 PIIX4芯片逻辑框图6.1.1 概述PIIX4芯片是一个多功能的PCI器件，图6-2 是82371在系统中扮演的角色。（续上图）1. PCI与EIO之间的桥（PIIX4芯片）桥是不对程的，是各类不同标准总线与PCI总线连接，82371AB桥也可理解为一种总线转换译码器和控制器，桥内包含复杂的协议总线信号和缓冲器。(1).在PCI系统内，当PIIX4操作时，它总是作为系统内各种模块的主控设备，如USB和DMA控制器、IDE总线和分布式DMA的主控设备等，而且总是以ISA主控设备的名义出现。(2). 在向ISA总线或IDE总线进行传送操作的传送周期期间作为从属设备使用，并对内部寄存器译码。PIIX4芯片（桥）的配置(1).可以把PIIX4芯片配置成整个ISA总线，或ISA总线的子集，也可扩展成EIO总线。在使用EIO总线时，可以把未使用的信号配置成通用的输入和输出。(2).PIIX4可直接驱动5个ISA插槽；(3).能提供字节-交换逻辑、I/O的恢复支持、等待状态的生成以及SYSCLK的生成。(4).提供X-BUS键盘控制器芯片、BIOS芯片、实时时钟芯片、二级微程序器等的选择。2. IDE接口（总线主控设备的权利和同步DMA方式）IDE接口为4个IDE的设备提供支持，比如IDE接口的硬盘和CD-ROM等。注意：目前硬盘接口有5类：IDE、SCSI、Fibre Channel、IEEE1394和USB等。IDE口几乎在PC机最多，因为便宜。SCSI多用于服务器和集群机。IDE的PIO IDE速率：14MB/s；而总线主控设备IDE的速率：33MB/s在PIIX4芯片的IDE系统内，配有两个各次独立的IDE信号通道。3. 具有兼容性的模块—DMA、定时器/计数器、中断控制器等（1）在PIIX4内的两各82C37 DMA控制器经逻辑的组合，产生7个独立的可编程通道。通道[0：3]是通过与8个二进位的硬件连线实现的。通过以字节为单位的计数进行传送。而通道[5：7]是通过16个二进位的连线实现的，以字为单位的计数进行传送。（2）DMA控制器还能通过PCI总线，处理旧的DMA的两个不同的方法提供支持。（3）计数/定时器模块在功能上与82C54等价。（4）中断控制器与ISA兼容，其功能是两个82C59的功能之和。
上传时间： 2013-11-19
上传用户：3到15
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
标签： synchronous Emulating serial
上传时间： 2014-01-31
上传用户：z1191176801
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上传时间： 2013-10-08
上传用户：18711024007
The μPSD32xx family, from ST, consists of Flash programmable system devices with a 8032 MicrocontrollerCore. Of these, the μPSD3234A and μPSD3254A are notable for having a complete implementationof the USB hardware directly on the chip, complying with the Universal Serial Bus Specification, Revision1.1.This application note describes a demonstration program that has been written for the DK3200 hardwaredemonstration kit (incorporating a μPSD3234A device). It gives the user an idea of how simple it is to workwith the device, using the HID class as a ready-made device driver for the USB connection.IN-APPLICATION-PROGRAMMING (IAP) AND IN-SYSTEM-PROGRAMMING (ISP)Since the μPSD contains two independent Flash memory arrays, the Micro Controller Unit (MCU) can executecode from one memory while erasing and programming the other. Product firmware updates in thefield can be reliably performed over any communication channel (such as CAN, Ethernet, UART, J1850)using this unique architecture. For In-Application-Programming (IAP), all code is updated through theMCU. The main advantage for the user is that the firmware can be updated remotely. The target applicationruns and takes care on its own program code and data memory.IAP is not the only method to program the firmware in μPSD devices. They can also be programmed usingIn-System-Programming (ISP). A IEEE1149.1-compliant JTAG interface is included on the μPSD. Withthis, the entire device can be rapidly programmed while soldered to the circuit board (Main Flash memory,Secondary Boot Flash memory, the PLD, and all configuration areas). This requires no MCU participation.The MCU is completely bypassed. So, the μPSD can be programmed or reprogrammed any time, anywhere, even when completely uncommitted.Both methods take place with the device in its normal hardware environment, soldered to a printed circuitboard. The IAP method cannot be used without previous use of ISP, because IAP utilizes a small amountof resident code to receive the service commands, and to perform the desired operations.
标签： Demonstration 3200 USB for
上传时间： 2014-02-27
上传用户：zhangzhenyu
The XA-S3 is a member of Philips Semiconductors’ XA (eXtended Architecture) family of high performance 16-bit single-chip Microcontrollers. The XA-S3 combines many powerful peripherals on one chip. Therefore, it is suited for general multipurpose high performance embedded control functions.One of the on-chip peripherals is the I2C bus interface. This report describes worked-out driver software (written in C) to program / use the I2C interface of the XA-S3. The driver software, together with a demo program and interface software routines offer the user a quick start in writing a complete I2C - XAS3 system application.
上传时间： 2013-11-10
上传用户：liaofamous
计算机部件要具有通用性，适应不同系统与不同用户的需求，设计必须模块化。计算机部件产品(模块)供应出现多元化。模块之间的联接关系要标准化，使模块具有通用性。模块设计必须基于一种大多数厂商认可的模块联接关系，即一种总线标准。总线的标准总线是一类信号线的集合是模块间传输信息的公共通道，通过它，计算机各部件间可进行各种数据和命令的传送。为使不同供应商的产品间能够互换，给用户更多的选择，总线的技术规范要标准化。总线的标准制定要经周密考虑，要有严格的规定。总线标准（技术规范）包括以下几部分：机械结构规范：模块尺寸、总线插头、总线接插件以及按装尺寸均有统一规定。功能规范：总线每条信号线（引脚的名称）、功能以及工作过程要有统一规定。电气规范：总线每条信号线的有效电平、动态转换时间、负载能力等。总线的发展情况S-100总线：产生于1975年，第一个标准化总线，为微计算机技术发展起到了推动作用。IBM-PC个人计算机采用总线结构（Industry Standard Architecture, ISA)并成为工业化的标准。先后出现8位ISA总线、16位ISA总线以及后来兼容厂商推出的EISA（Extended ISA)32位ISA总线。为了适应微处理器性能的提高及I/O模块更高吞吐率的要求，出现了VL-Bus(VESA Local Bus)和PCI(Peripheral Component Interconnect,PCI）总线。适合小型化要求的PCMCIA(Personal Computer Memory Card International Association)总线，用于笔记本计算机的功能扩展。总线的指标计算机主机性能迅速提高,各功能模块性能也要相应提高,这对总线性能提出更高的要求。总线主要技术指标有几方面：总线宽度：一次操作可以传输的数据位数，如S100为8位，ISA为16位，EISA为32位，PCI-2可达64位。总线宽度不会超过微处理器外部数据总线的宽度。总数工作频率：总线信号中有一个CLK时钟，CLK越高每秒钟传输的数据量越大。ISA、EISA为8MHz，PCI为33.3MHz, PCI-2可达达66.6MHz。单个数据传输周期：不同的传输方式，每个数据传输所用CLK周期数不同。ISA要2个，PCI用1个CLK周期。这决定总线最高数据传输率。5. 总线的分类与层次系统总线：是微处理器芯片对外引线信号的延伸或映射，是微处理器与片外存储器及I/0接口传输信息的通路。系统总线信号按功能可分为三类：地址总线（Where）：指出数据的来源与去向。地址总线的位数决定了存储空间的大小。系统总线：数据总线（What）提供模块间传输数据的路径，数据总线的位数决定微处理器结构的复杂度及总体性能。控制总线（When）：提供系统操作所必需的控制信号，对操作过程进行控制与定时。扩充总线：亦称设备总线，用于系统I/O扩充。与系统总线工作频率不同，经接口电路对系统总统信号缓冲、变换、隔离，进行不同层次的操作（ISA、EISA、MCA)局部总线：扩充总线不能满足高性能设备（图形、视频、网络）接口的要求，在系统总线与扩充总线之间插入一层总线。由于它经桥接器与系统总线直接相连，因此称之为局部总线（PCI）。
上传时间： 2013-11-09
上传用户：nshark
基于单片机的汽车多功能报警系统设计The Design of Automobile Multi-function AlarmingBased on Single Chip Computer刘法治赵明富宁睡达(河 南 科 技 学 院 ，新 乡 453 00 3)摘要介绍了一种基于单片机控制的汽车多功能报警系统，它能对汽车的润滑系统油压、制动系统气压、冷却系统温度、轮胎欠压及防盗进行自动检测，并在发现异常情况时，发出声光报警。阐述了该报警系统的硬件组成及软件设计方法。关键词单片机传感器数模转换报警Abstract Am ulti-fimctiona utomobilea larnungs ystemb asedo ns inglec hipc omputerco ntorlis in torducedin th isp aper.Th eo ilpr essuero flu bricatesystem, air pressure of braking system, temperature of cooling system, under pressure of tyre and guard against theft， detected automaticaly场thesystem. Audio and visual alarms wil be provided under abnormal conditions厂The hardware composition and software design of the system， described.Keywords Singlec hipc omputer Sensor Digital-t-oanaloguec onversion Alarmin 汽车多功能报苦器硬件系统设计根据 系 统 实际需要和产品性价比，选用ATMEL公司新生产的采用CMOs工艺的低功耗、高性能8位单片机AT89S52作为系统的控制器。AT89S52的片内有8k Bytes LSP Flash闪烁存储器，可进行100(〕次写、擦除操作;256Bytes内部数据存储器(RAM);3 2 根可编程输N输出线;2个可编程全双工串行通道;看门狗(WTD)电路等。系统由传感器、单片机、模数转换器、无线信号发射电路、指示灯驱动电路、声光报警驱动电KD一9563，发出三声二闪光。并触发一个高电平，驱动无线信号发射电路。
上传时间： 2013-11-09
上传用户：gxmm
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上传时间： 2014-12-28
上传用户：zhang97080564
WP369可扩展式处理平台-各种嵌入式系统的理想解决方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
上传时间： 2013-10-22
上传用户：685
