We have a group of N items (represented by integers from 1 to N), and we know that there is some total order defined for these items. You may assume that no two elements will be equal (for all a, b: a<b or b<a). However, it is expensive to compare two items. Your task is to make a number of comparisons, and then output the sorted order. The cost of determining if a < b is given by the bth integer of element a of costs (space delimited), which is the same as the ath integer of element b. Naturally, you will be judged on the total cost of the comparisons you make before outputting the sorted order. If your order is incorrect, you will receive a 0. Otherwise, your score will be opt/cost, where opt is the best cost anyone has achieved and cost is the total cost of the comparisons you make (so your score for a test case will be between 0 and 1). Your score for the problem will simply be the sum of your scores for the individual test cases.
标签： represented integers group items
上传时间： 2016-01-17
上传用户：jeffery
嵌入式程序，实现了在altera FPGA DE2上面的 micro/us 实时操作系统，几个任务间的互相转换，以及时间的控制。
标签： 嵌入式程序
上传时间： 2013-12-19
上传用户：13188549192
hdb3的发送端源代码，采用verilog可综合格式书写。已经在多款fpga和cpld芯片成功综合实现。
上传时间： 2013-12-26
上传用户：924484786
The XML Toolbox converts MATLAB data types (such as double, char, struct, complex, sparse, logical) of any level of nesting to XML format and vice versa. For example, >> project.name = MyProject >> project.id = 1234 >> project.param.a = 3.1415 >> project.param.b = 42 becomes with str=xml_format(project, off ) "<project> <name>MyProject</name> <id>1234</id> <param> <a>3.1415</a> <b>42</b> </param> </project>" On the other hand, if an XML string XStr is given, this can be converted easily to a MATLAB data type or structure V with the command V=xml_parse(XStr).
标签： converts Toolbox complex logical
上传时间： 2016-02-12
上传用户：a673761058
采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置，源代码对FPGA和CPLD学习者价值很高，
上传时间： 2016-03-21
上传用户：270189020
VHDL书写VGA源码，可用于FPGA和CPLD
上传时间： 2016-05-23
上传用户：xwd2010
：介绍一种仅使用配置空间设计PCI板卡的方法，使扳卡设计者能比较客易从ISA过渡到 PCI设计，该方法基于FPGA／CPLD，在最小设计模式下，仅使用18个引脚就能实现简易的眦功能 卡。
上传时间： 2014-01-15
上传用户：凤临西北
SD card controller can just read data using 1 bit SD mode. I have written this core for NIOS2 CPU, Cyclone, but I think it can works with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core. Good luck
标签： controller written NIOS2 using
上传时间： 2016-08-12
上传用户：王楚楚
QuartusII简介手册+中文版 本手册针对的读者是 Quartus II 软件的初学者，它概述了可编程逻辑设计中 Quartus II 软件的功能。 不过，本手册并不是 Quartus II 软件的详尽参考手 册。 相反，本手册只是一本指导书，它解释软件的功能以及显示这些功能如 何帮助您进行 FPGA 和 CPLD 设计。
上传时间： 2013-12-21
上传用户：hj_18
一个FIFO源代码，基于Altera FPGA
上传时间： 2014-01-24
上传用户：王者A
