The PCA9674/74A is a drop-in upgrade for the PCF8574/74A providing higher Fast-modePlus I2C-bus speeds (1 MHz versus 400 kHz) so thAT the output can support PWMdimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so thAT many more devicescan be on the bus without the need for bus buffers, higher total package sink capacity(200 mA versus 100 mA) thAT supports having all LEDs on AT the same time and moredevice addresses (64 versus 8) are available to allow many more devices on the buswithout address conflicts.
上传时间： 2013-10-22
上传用户：wwwwwen5
The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communicATion controller and the serial-port connector. ThiscombinATion of drivers and receivers mATches thAT needed for the typical serial port used in an IBM PC/AT, orcompATible. The charge pump and four small external capacitors allow operATion from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-active noninverting output (ROUT2B), which allowsapplicATions using the ring indicATor to transmit dATa while the device is powered down. The device operATes ATdATa signaling rATes up to 250 kbit/s and a maximum of 30-V/ms driver output slew rATe.
标签： MULTICHANNEL 5.5 TO RS
上传时间： 2013-10-19
上传用户：ddddddd
The Philips family of Multiplexers and Switches consists of bi-directional translATing switches controlled via the I2C or SMBus to fan out an upstream SCL/SDA pair to 2, 4 or 8 downstream channels of SCx/SDx pairs. The Multiplexers allow only one downstream channel to be selected AT a time, while the Switches allow any individual downstream channel or combinATion of downstream channels to be selected, depending on the content of the programmable control register. Once one or several channels have been selected, the device acts as a wire, allowing the master on the upstream channel to send commands to devices on all the active downstream channels, and devices on the active downstream channels to communicATe with each other and the master. External pull-up resistors are used to pull each individual channel up to the desired voltage level. Combined interrupt output and hardware reset input are device options thAT are feATured.
上传时间： 2013-10-11
上传用户：dianxin61
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulATion of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the ATtached source files emulATes the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% ATSAB C513 with 12 MHz. Due to the implementATion in C this performance is not the limitof the chip. A pure implementATion in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulATed interface.Due to the restricted performance of an 8 bit microcontroller a pin compATible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The ATtached source files also contain a test shell, which demonstrATes how to exchangeinformATion between an on-chip HW-SSC and the emulATed SW-SSC via 5 external wiresin different operATion modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indicATion for the fraction of CPUperformance required by software for emulATing the SSC.
标签： synchronous EmulATing serial
上传时间： 2014-01-31
上传用户：z1191176801
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplicATion to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care thAT rising/falling input signals pass the undefined area of theTTL-specificATion between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gATes 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is thAT even if the input signal remains inthe undefined area, well defined low/high levels are generATed internally. Note thAT allinput signals are evaluATed AT specific sample points (depending on the input and theperipheral function connected to it), AT thAT signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalAT these sample points is relevant, thAT means, the necessary rise/fall times of the inputsignal is only dependant on the sample rATe, thAT is the distance in time between twoconsecutive evaluATion time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rATe of 10us, it is assured thAT only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rATe is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rATe of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the ATtached diagram, the effect of the sample rATe is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling AT 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling AT 1, 2, 5,3, and 4).Sample points:1. EvaluATion of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriATe action (e.g. capture) might take place.3. EvaluATion here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, ATransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplicATion to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care thAT rising/falling input signals pass the undefined area of theTTL-specificATion between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gATes 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is thAT even if the input signal remains inthe undefined area, well defined low/high levels are generATed internally. Note thAT allinput signals are evaluATed AT specific sample points (depending on the input and theperipheral function connected to it), AT thAT signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalAT these sample points is relevant, thAT means, the necessary rise/fall times of the inputsignal is only dependant on the sample rATe, thAT is the distance in time between twoconsecutive evaluATion time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rATe of 10us, it is assured thAT only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rATe is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rATe of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
MPC7400 Part Number SpeciÞcATionThis document describes part number speciÞc changes to recommended operATing conditions and revised electrical speciÞcATions,as applicable, from those described in the generalMPC7400 Hardware SpeciÞcATions.SpeciÞcATions provided in this Part Number SpeciÞcATion supersede those in theMPC7400 Hardware SpeciÞcATionsdATed 9/99(order #: MPC7400EC/D) for these part numbers only; speciÞcATions not addressed herein are unchanged. This document isfrequently updATed, refer to the website AT http://www.mot.com/SPS/PowerPC/ for the lATest version.Note thAT headings and table numbers in this dATa sheet are not consecutively numbered. They are intended to correspond to theheading or table affected in the general hardware speciÞcATion.
上传时间： 2014-12-28
上传用户：huyahui
This document describes part number speciÞc changes to recommended operATing conditions and revised electrical speciÞcATions,as applicable, from those described in the generalMPC7400 Hardware SpeciÞcATions.SpeciÞcATions provided in this Part Number SpeciÞcATion supersede those in theMPC7400 Hardware SpeciÞcATionsdATed 9/99(order #: MPC7400EC/D) for these part numbers only; speciÞcATions not addressed herein are unchanged. This document isfrequently updATed, refer to the website AT http://www.mot.com/SPS/PowerPC/ for the lATest version.Note thAT headings and table numbers in this dATa sheet are not consecutively numbered. They are intended to correspond to theheading or table affected in the general hardware speciÞcATion.Part numbers addressed in this document are listed in Table A. For more detailed ordering informATion see Table B.
上传时间： 2013-11-19
上传用户：qiaoyue
当拿到一张CASE单时，首先得确定的是能用什么母体才能实现此功能，然后才能展开对外围硬件电路的设计，因此首先得了解每个母体的基本功能及特点，下面大至的介绍一下本公司常用的IC：单芯片解决方案• SN8P1900 系列– 高精度 16-Bit 模数转换器– 可编程运算放大器 (PGIA)• 信号放大低漂移: 2V• 放大倍数可编程: 1/16/64/128 倍– 升压- 稳压调节器 (Charge-Pump RegulATor)• 电源输入: 2.4V ~ 5V• 稳压输出: e.g. 3.8V AT SN8P1909– 内置液晶驱动电路 (LCD Driver)– 单芯片解决方案 • 耳温枪 SN8P1909 LQFP 80 Pins• 5000 解析度量测器 SN8P1908 LQFP 64 Pins• 体重计 SN8P1907 SSOP 48 Pins单芯片解决方案• SN8P1820 系列– 精确的12-Bit 模数转换器– 可编程运算放大器 (PGIA)• Gain Stage One: Low Offset 5V, Gain: 16/32/64/128• Gain Stage One: Low Offset 2mV, Gain: 1.3 ~ 2.5– 升压- 稳压调节器• 电源输入: 2.4V ~ 5V• 稳压输出: e.g. 3.8V AT SN8P1829– 内置可编程运算放大电路– 内置液晶驱动电路 – 单芯片解决方案 • 电子医疗器 SN8P1829 LQFP 80 Pins 高速/低功耗/高可靠性微控制器• 最新SN8P2000 系列– SN8P2500/2600/2700 系列– 高度抗交流杂讯能力• 标准瞬间电压脉冲群测试 (EFT): IEC 1000-4-4• 杂讯直接灌入芯片电源输入端• 只需添加1颗 2.2F/50V 旁路电容• 测试指标稳超 4000V (欧规)– 高可靠性复位电路保证系统正常运行• 支持外部复位和内部上电复位• 内置1.8V 低电压侦测可靠复位电路• 内置看门狗计时器保证程序跳飞可靠复位– 高抗静电/栓锁效应能力– 芯片工作温度有所提高: -200C ~ 700C 工规芯片温度： -400C ~ 850C 高速/低功耗/高可靠性微控制器• 最新 SN8P2000 系列– SN8P2500/2600/2700 系列– 1T 精简指令级结构• 1T: 一个外部振荡周期执行一条指令• 工作速度可达16 MIPS / 16 MHz Crystal– 工作消耗电流 < 2mA AT 1-MIPS/5V– 睡眠模式下消耗电流 < 1A / 5V额外功能• 高速脉宽调制输出 (PWM)– 8-Bit PWM up to 23 KHz AT 12 MHz System Clock– 6-Bit PWM up to 93 KHz AT 12 MHz System Clock– 4-Bit PWM up to 375 KHz AT 12 MHz System Clock• 内置高速16 MHz RC振荡器 (SN8P2501A)• 电压变化唤醒功能• 可编程控制沿触发/中断功能– 上升沿 / 下降沿 / 双沿触发• 串行编程接口
上传时间： 2013-10-21
上传用户：jiahao131
//芯片资料请到www.elecfans.com查找 //DS1820 C51 子程序//这里以11.0592M晶体为例，不同的晶体速度可能需要调整延时的时间//sbit DQ =P2^1;//根据实际情况定义端口 typedef unsigned char byte;typedef unsigned int word; //延时void delay(word useconds){ for(;useconds>0;useconds--);} //复位byte ow_reset(void){ byte presence; DQ = 0; //pull DQ line low delay(29); // leave it low for 480us DQ = 1; // allow line to return high delay(3); // wait for presence presence = DQ; // get presence signal delay(25); // wait for end of timeslot return(presence); // presence signal returned} // 0=presence, 1 = no part //从 1-wire 总线上读取一个字节byte read_byte(void){ byte i; byte value = 0; for (i=8;i>0;i--) { value>>=1; DQ = 0; // pull DQ low to start timeslot DQ = 1; // then return high delay(1); //for (i=0; i<3; i++); if(DQ)value|=0x80; delay(6); // wait for rest of timeslot } return(value);} //向 1-WIRE 总线上写一个字节void write_byte(char val){ byte i; for (i=8; i>0; i--) // writes byte, one bit AT a time { DQ = 0; // pull DQ low to start timeslot DQ = val&0x01; delay(5); // hold value for remainder of timeslot DQ = 1; val=val/2; } delay(5);} //读取温度char Read_TemperATure(void){ union{ byte c[2]; int x; }temp; ow_reset(); write_byte(0xCC); // Skip ROM write_byte(0xBE); // Read ScrATch Pad temp.c[1]=read_byte(); temp.c[0]=read_byte(); ow_reset(); write_byte(0xCC); //Skip ROM write_byte(0x44); // Start Conversion return temp.x/2;}
上传时间： 2013-11-03
上传用户：hongmo
