Nios II 软件开发人员手册中的缓存和紧耦合存储器部分 Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II ARCHITECTURE provides facilities to perform the following actions:
上传时间： 2013-10-25
上传用户：虫虫虫虫虫虫
The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying ARCHITECTURE is a traditional CPLD ARCHITECTURE, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.
上传时间： 2013-11-03
上传用户：1037540470
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ ARCHITECTURE to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上传时间： 2013-12-07
上传用户：bruce
WP369可扩展式处理平台-各种嵌入式系统的理想解决方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's ARCHITECTURE for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
上传时间： 2013-10-18
上传用户：cursor
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an ARCHITECTURE where the part is externally programmed?
上传时间： 2013-10-20
上传用户：磊子226
针对嵌入式机器视觉系统向独立化、智能化发展的要求，介绍了一种嵌入式视觉系统--智能相机。基于对智能相机体系结构、组成模块和图像采集、传输和处理技术的分析，对国内外的几款智能相机进行比较。综合技术发展现状，提出基于FPGA+DSP模式的硬件平台，并提出智能相机的发展方向。分析结果表明，该系统设计可以实现脱离PC运行，完成图像获取与分析，并作出相应输出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera ARCHITECTURE， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
上传时间： 2013-11-14
上传用户：无聊来刷下
ref-sdr-sdram-vhdl代码 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen ARCHITECTURE. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上传时间： 2013-10-23
上传用户：半熟1994
ISA总线概述 ISA总线: (Industry Standard ARCHITECTURE:工业标准体系结构）是IBM公司为PC/AT电脑而制定的总线标准，为16位体系结构，只能支持16位的I/O设备，数据传输率大约是16MB/S。也称为AT标准。开始时PC机面向个人及办公室，定义了8位的ISA总线结构，对外公开，成为标准（ISO ISA标准）。第三方开发出许多ISA扩充板卡，推动了PC机的发展。1984年推出IBM-PC/AT系统，ISA从8位扩充到16位，地址线从20条扩充到24条。1988年，康柏、HP、NEC等9个厂商协同把ISA扩展到32位，即EISA总线(Extended ISA)。
上传时间： 2013-10-16
上传用户：dajin
XMDS is a code generator that integrates equations. You write them down in human readable form in a XML file, and it goes away and writes and compiles a C++ program that integrates those equations as fast as it can possibly be done in your ARCHITECTURE.
标签： integrates generator equations readable
上传时间： 2014-11-27
上传用户：hebmuljb
ava加密扩展即Java Cryptography Extension，简称JCE。它是Sun的加密服务软件，包含了加密和密匙生成功能。JCE是JCA（Java Cryptography ARCHITECTURE）的一种扩展。 JCE没有规定具体的加密算法，但提供了一个框架，加密算法的具体实现可以作为服务提供者加入。除了JCE框架之外，JCE软件包还包含了SunJCE服务提供者，其中包括许多有用的加密算法，比如DES（Data Encryption Standard）和Blowfish。 为简单计，在本文中我们将用DES算法加密和解密字节码。下面是用JCE加密和解密数据必须遵循的基本步骤： 步骤1：生成一个安全密匙。在加密或解密任何数据之前需要有一个密匙。密匙是随同被加密的应用一起发布的一小段数据，Listing 3显示了如何生成一个密匙。 【Listing 3：生成一个密匙】
标签： Cryptography Extension Java ava
上传时间： 2015-03-26
上传用户：nanxia
