The fi rst edition of this book came about because Regina Lundgren had ALWAYS been fascinated with communication. She started writing novels in the third grade. When she was asked on her fi rst day at the University of Washington what she hoped to do with her degree in scientifi c and technical communication, she replied, “I want to write environ- mental impact statements.” When Patricia Clark hired her to work at the Pacifi c Northwest National Laboratory to do just that, she was overjoyed.
标签： COMMUNICATION RISK
上传时间： 2020-06-01
上传用户：shancjb
The first question most readers of an O’Reilly book might ask is about the choice of the cover animal. In this case, “why a duck?” Well, for the record, our first choice was a unicorn decked out in glitter and a rainbow sash. That response ALWAYS gets a laugh (we are sure you just giggled a little), but it also brings to the surface a common perception of software-defined networks among many expe‐ rienced network professionals. Although we think there is some truth to this perception, there is certainly more meat than myth to this unicorn.
标签： Networks Software Defined SDN
上传时间： 2020-06-01
上传用户：shancjb
It all started rather innocuously. I walked into Dr GT Murthy’s office one fine day, andchanged my life. “Doc” was then the General Manager, Central R&D, of a very largeelectrical company headquartered in Bombay. In his new state-of-the-art electronics center,he had hand-picked some of India’s best engineers (over a hundred already) ever assembledunder one roof. Luckily, he too was originally a Physicist, and that certainly helped me gainsome empathy. Nowadays he is in retirement, but I will ALWAYS remember him as athoroughly fair, honest and facts-oriented person, who led by example. There were severalthings I absorbed from him that are very much part of my basic engineering persona today.You can certainly look upon this book as an extension of what Doc started many years agoin India … because that’s what it really is! I certainly wouldn’t be here today if I hadn’t metDoc. And in fact, several of the brash, high-flying managers I’ve met in recent years,desperately need some sort of crash course in technology and human values from Doc!
标签： 开关电源
上传时间： 2021-11-23
上传用户：
FPGA片内FIFO读写测试Verilog逻辑源码Quartus工程文件+文档说明，使用 FPGA 内部的 FIFO 以及程序对该 FIFO 的数据读写操作。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz时钟 input rst_n //复位信号，低电平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO写数据wire wr_en; //FIFO写使能wire rd_en; //FIFO读使能wire[15:0] r_data; //FIFO读数据wire full; //FIFO满信号 wire empty; //FIFO空信号 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///产生FIFO写入的数据ALWAYS@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endALWAYS@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空， 开始写FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO满 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; ALWAYS@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///产生FIFO读的数据ALWAYS@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endALWAYS@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO满, 开始读FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)
上传时间： 2021-12-19
上传用户：20125101110
实验教学一直是工科教学中不可或缺的组成部分,对培养学生的动手能力,独立思考能力,创新思维与发散思维具有重要的作用。针对目前电路教学实验中电路仿真实验与实物电路实验各自独立,无法统一问题,提出将仿真电路实验与实物电路实验有机的结合同步操作,并使用Web发布实现远程实验操作。采用Multisim作为电路实验仿真平台,NI Eiviss II作为实物电路实验硬件平台,运用LabVIEW整合Multisim电路仿真实验与实物电路实验,实现仿真与实物实验有机结合,两种实验可同步进行。学生在仿真实验中先可探索实验,然后做实物实验。同时运用LabVIEW开发出实验过程人机交互操作接口界面,使用过程中效果良好。Experimental teaching has ALWAYS been an indispensable part of engineering education.And it ALWAYS plays an important role in cultivating students'practical ability,independent thinking ability,innovative thinking and divergent thinking.But simulation experiment and physical experiment cannot be unified in the circuit teaching experiment at present.In order to solve this problem,this paper proposes to combine organically the simulation circuit experiment with physical circuit experiment,and synchronously operate them.This paper uses the WEB publishing to achieve remote experimental operation.Multisim is used as the circuit simulation platform,and NI Eiviss II is used as the physical circuit hardware platform.Multisim circuit simulation experiment and physical circuit experiment are implemented by LabVIEW to realize the combination of simulation experiment and physical experiment.Students do explore experiments in simulation experiment firstly,and then do physical experiment.And this paper uses LabVIEW to develop the experimental man-machine interface.
上传时间： 2022-04-05
上传用户：
【例3.1]4位全加器module adder 4（cout，sum i na，i nb，cin）；output[3：0]sum output cout；input[3：0]i na，i nb；input cin；assign（cout，suml=i na +i nb+ci n；endmodule【例3.2]4位计数器module count 4（out，reset，clk）；output[3：0]out；input reset，cl k；regl 3：01 out；ALWAYS@posedge clk）
标签： verilog
上传时间： 2022-06-16
上传用户：canderile
