All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
摘要: 串行传输技术具有更高的传输速率和更低的设计成本, 已成为业界首选, 被广泛应用于高速通信领域。提出了一种新的高速串行传输接口的设计方案, 改进了Aurora 协议数据帧格式定义的弊端, 并采用高速串行收发器Rocket I/O, 实现数据率为2.5 Gbps的高速串行传输。关键词: 高速串行传输; Rocket I/O; Aurora 协议 为促使FPGA 芯片与串行传输技术更好地结合以满足市场需求, Xilinx 公司适时推出了内嵌高速串行收发器RocketI/O 的Virtex II Pro 系列FPGA 和可升级的小型链路层协议———Aurora 协议。Rocket I/O支持从622 Mbps 至3.125 Gbps的全双工传输速率, 还具有8 B/10 B 编解码、时钟生成及恢复等功能, 可以理想地适用于芯片之间或背板的高速串行数据传输。Aurora 协议是为专有上层协议或行业标准的上层协议提供透明接口的第一款串行互连协议, 可用于高速线性通路之间的点到点串行数据传输, 同时其可扩展的带宽, 为系统设计人员提供了所需要的灵活性[4]。但该协议帧格式的定义存在弊端,会导致系统资源的浪费。本文提出的设计方案可以改进Aurora 协议的固有缺陷,提高系统性能, 实现数据率为2.5 Gbps 的高速串行传输, 具有良好的可行性和广阔的应用前景。
上传时间： 2013-11-06
上传用户：smallfish
摘要: 串行传输技术具有更高的传输速率和更低的设计成本, 已成为业界首选, 被广泛应用于高速通信领域。提出了一种新的高速串行传输接口的设计方案, 改进了Aurora 协议数据帧格式定义的弊端, 并采用高速串行收发器Rocket I/O, 实现数据率为2.5 Gbps的高速串行传输。关键词: 高速串行传输; Rocket I/O; Aurora 协议 为促使FPGA 芯片与串行传输技术更好地结合以满足市场需求, Xilinx 公司适时推出了内嵌高速串行收发器RocketI/O 的Virtex II Pro 系列FPGA 和可升级的小型链路层协议———Aurora 协议。Rocket I/O支持从622 Mbps 至3.125 Gbps的全双工传输速率, 还具有8 B/10 B 编解码、时钟生成及恢复等功能, 可以理想地适用于芯片之间或背板的高速串行数据传输。Aurora 协议是为专有上层协议或行业标准的上层协议提供透明接口的第一款串行互连协议, 可用于高速线性通路之间的点到点串行数据传输, 同时其可扩展的带宽, 为系统设计人员提供了所需要的灵活性[4]。但该协议帧格式的定义存在弊端,会导致系统资源的浪费。本文提出的设计方案可以改进Aurora 协议的固有缺陷,提高系统性能, 实现数据率为2.5 Gbps 的高速串行传输, 具有良好的可行性和广阔的应用前景。
上传时间： 2013-10-13
上传用户：lml1234lml
Cantor 表问题： 问题描述： 把分子和分母均小于108 的分数按下面的办法排成一个数表。 1/1 1/2 1/3 1/4 1/5 ... 2/1 2/2 2/3 2/4 2/5 ... 3/1 3/2 3/3 3/4 3/5 ... 4/1 4/2 4/3 4/4 4/5 ... 5/1 5/2 5/3 5/4 5/5 ... ... ... 我们以Z 方形方法给上表的每项编号。第一项是1/1，第二项是1/2， 然后是2/1，3/1，2/2，1/3，1/4，2/3，3/2，4/1，5/1，4/2，...... 要求:对于给定的输入的编号N(0<N<10000)，能够输出其中的第N 项。 如： 输入N = 7； 输出1/4。
上传时间： 2015-02-14
上传用户：hasan2015
RSA算法 :首先, 找出三个数, p, q, r, 其中 p, q 是两个相异的质数, r 是与 (p-1)(q-1) 互质的数...... p, q, r 这三个数便是 person_key，接著, 找出 m, 使得 r^m == 1 mod (p-1)(q-1)..... 这个 m 一定存在, 因为 r 与 (p-1)(q-1) 互质, 用辗转相除法就可以得到了..... 再来, 计算 n = pq....... m, n 这两个数便是 public_key ，编码过程是, 若资料为 a, 将其看成是一个大整数, 假设 a < n.... 如果 a >= n 的话, 就将 a 表成 s 进位 (s
标签： person_key RSA 算法
上传时间： 2013-12-14
上传用户：zhuyibin
* 高斯列主元素消去法求解矩阵方程AX=B,其中A是N*N的矩阵,B是N*M矩阵 * 输入: n----方阵A的行数 * a----矩阵A * m----矩阵B的列数 * b----矩阵B * 输出: det----矩阵A的行列式值 * a----A消元后的上三角矩阵 * b----矩阵方程的解X
上传时间： 2015-07-26
上传用户：xauthu
一:需求分析 1. 问题描述 魔王总是使用自己的一种非常精练而抽象的语言讲话,没人能听懂,但他的语言是可逐步解释成人能听懂的语言,因为他的语言是由以下两种形式的规则由人的语言逐步抽象上去的: ----------------------------------------------------------- (1) a---> (B1)(B2)....(Bm) (2)[(op1)(p2)...(pn)]---->[o(pn)][o(p(n-1))].....[o(p1)o] ----------------------------------------------------------- 在这两种形式中,从左到右均表示解释.试写一个魔王语言的解释系统,把 他的话解释成人能听得懂的话. 2. 基本要求: 用下述两条具体规则和上述规则形式(2)实现.设大写字母表示魔王语言的词汇 小写字母表示人的语言的词汇 希腊字母表示可以用大写字母或小写字母代换的变量.魔王语言可含人的词汇. (1) B --> tAdA (2) A --> sae 3. 测试数据: B(ehnxgz)B 解释成 tsaedsaeezegexenehetsaedsae若将小写字母与汉字建立下表所示的对应关系,则魔王说的话是:"天上一只鹅地上一只鹅鹅追鹅赶鹅下鹅蛋鹅恨鹅天上一只鹅地上一只鹅". | t | d | s | a | e | z | g | x | n | h | | 天 | 地 | 上 | 一只| 鹅 | 追 | 赶 | 下 | 蛋 | 恨 |
上传时间： 2014-12-02
上传用户：jkhjkh1982
We have a group of N items (represented by integers from 1 to N), and we know that there is some total order defined for these items. You may assume that no two elements will be equal (for all a, b: a<b or b<a). However, it is expensive to compare two items. Your task is to make a number of comparisons, and then output the sorted order. The cost of determining if a < b is given by the bth integer of element a of costs (space delimited), which is the same as the ath integer of element b. Naturally, you will be judged on the total cost of the comparisons you make before outputting the sorted order. If your order is incorrect, you will receive a 0. Otherwise, your score will be opt/cost, where opt is the best cost anyone has achieved and cost is the total cost of the comparisons you make (so your score for a test case will be between 0 and 1). Your score for the problem will simply be the sum of your scores for the individual test cases.
标签： represented integers group items
上传时间： 2016-01-17
上传用户：jeffery
古典密码中，主要的思想为移位算法及置换算法。 1.移位密码 密钥K为整数，且取值空间为0到25；加密函数：x = x + k (mod 26)；解密函数：x = x - k (mod 26)。当K=3时，为凯撒密码。 2.仿射密码 密钥对由a、b组成，整数a满足 gcd(a, 26) = 1，整数b的取值空间为0到25；加密函数：x = ax + b(mod 26)；解密函数：x = a*y - a*b (mod 26)。当a=1,b=3时，为凯撒密码。 3.维吉尼亚密码 首先确定密钥长度（本例中密钥只采取个位数字，所以取决于输入密钥的长度），然后输入满足这个长度的向量；加密：取明文第一个字母并将之移k1位，这里k1=1,第二个字母移k2位，k2=2,一旦到了密钥末尾，又从头开始。 4.换位密码 首先确定密钥长度，输入长度为5的0到4的整数序列，将明文分成每5个字母一组，每组字母按照密钥进行换位。
标签： 密码
上传时间： 2016-02-09
上传用户：jqy_china
MySQL 5.1参考手册 这是MySQL参考手册的翻译版本，关于MySQL参考手册，请访问dev.mysql.com。 原始参考手册 为英文版，与英文版参考手册相比，本翻译版可能不是最新的。 摘要 这是MySQL参考手册 它涉及MySQL 5.1至5.1.2-alpha版本。 文档生成于： 2005-11-15
上传时间： 2013-12-09
上传用户：Breathe0125
