摘要：介绍一种以8031单片机组成的流水线产量红外计数装置，着重讨论了它的外围硬件电路和软件设计思想。关键词：8031单片机 流水 红外 计数
上传时间： 2014-10-28
上传用户：daguogai
几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码
上传时间： 2013-12-02
上传用户：jyycc
verilog编写的流水线模块
上传时间： 2015-03-09
上传用户：杜莹12345
遗传算法计算一条流水线作业时间问题的matlab程序代码
上传时间： 2014-12-07
上传用户：lizhen9880
计算机体系结构中关于通用5级流水线的模拟实现程序
上传时间： 2014-01-13
上传用户：ljt101007
能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术
上传时间： 2013-12-06
上传用户：aa17807091
利用arm指令流水线提高代码执行效率，大概能提升20％左右；缺点是增加了代码长度
上传时间： 2015-04-24
上传用户：qoovoop
推荐下载,verilog状态机实例.体现了流水线思想的应用
上传时间： 2014-01-25
上传用户：1101055045
大型risc处理器设计源代码,这是书中的代码 基于流水线的risc cpu设计
上传时间： 2014-12-05
上传用户：myworkpost
关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
标签： investigates implementing pipelines circuits
上传时间： 2015-07-26
上传用户：CHINA526
