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代码大全

  • Protel DXP常用封装库大全

    Protel+DXP+常用封装库大全

    标签: Protel DXP 封装库

    上传时间: 2013-10-22

    上传用户:superman111

  • FIFO的verilog代码

    FIFO的verilog代码

    标签: verilog FIFO 代码

    上传时间: 2013-12-22

    上传用户:ccxzzhm

  • altium designer元件库大全

    altium designer元件库大全

    标签: designer altium 元件库

    上传时间: 2013-10-26

    上传用户:标点符号

  • protel99se.快捷键大全

    protel99se.快捷键大全l

    标签: protel 99 se 快捷键

    上传时间: 2013-11-11

    上传用户:aa17807091

  • 元器件封装规格大全

    元器件封装规格大全

    标签: 元器件 封装规格

    上传时间: 2013-10-21

    上传用户:66666

  • protel快捷键大全

    protel快捷键大全

    标签: protel 快捷键

    上传时间: 2013-10-11

    上传用户:ippler8

  • ZBT SRAM控制器参考设计,xilinx提供VHDL代码

    ZBT SRAM控制器参考设计,xilinx提供VHDL代码 Description:   Contains the following files     readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform:   All Installation/Use:   Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.

    标签: xilinx SRAM VHDL ZBT

    上传时间: 2013-10-25

    上传用户:peterli123456

  • USB接口控制器参考设计,xilinx提供VHDL代码 us

    USB接口控制器参考设计,xilinx提供VHDL代码 usb xilinx vhdl ;  This program is free software; you can redistribute it and/or modify ;  it under the terms of the GNU General Public License as published by ;  the Free Software Foundation; either version 2 of the License, or ;  (at your option) any later version. ;      ;  This program is distributed in the hope that it will be useful, ;  but WITHOUT ANY WARRANTY; without even the implied warranty of ;  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the ;  GNU General Public License for more details. ;      ;  You should have received a copy of the GNU General Public License ;  along with this program; if not, write to the Free Software ;  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

    标签: xilinx VHDL USB us

    上传时间: 2013-10-29

    上传用户:zhouchang199

  • ref sdr sdram vhdl代码

    ref-sdr-sdram-vhdl代码 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.

    标签: sdram vhdl ref sdr

    上传时间: 2013-10-23

    上传用户:半熟1994

  • UART 4 UART参考设计,Xilinx提供VHDL代码

    UART 4 UART参考设计,Xilinx提供VHDL代码 uart_vhdl This zip file contains the following folders:  \vhdl_source  -- Source VHDL files:      uart.vhd  - top level file      txmit.vhd - transmit portion of uart      rcvr.vhd -  - receive portion of uart \vhdl_testfixture  -- VHDL Testbench files. This files only include the testbench behavior, they         do not instantiate the DUT. This can easily be done in a top-level VHDL          file or a schematic. This folder contains the following files:      txmit_tb.vhd  -- Test bench for txmit.vhd.      rcvr_tf.vhd  -- Test bench for rcvr.vhd.

    标签: UART Xilinx VHDL 参考设计

    上传时间: 2013-11-02

    上传用户:18862121743