代码搜索：when
找到约 10,000 项符合「when」的源代码
代码结果 10,000
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vhd lcd.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lcd is
generic ( asciiwidth : positive := 8);
port ( clk : in
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txt 新建 文本文档 (3).txt
--*********************************************
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
LIBRARY altera;
USE altera.
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vhd keys_test.vhd
--*********************************************
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
--
--*****************************
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vhd dds_vhdl.vhd
--主程序
--程序名
library ieee;
use ieee.std_logic_1164.all;
entity frqload is
port(num:in std_logic_vector(3 downto 0);
q:out integer range 0 to 312);
end frqload;
architecture a of frqload
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bak ps2_mouse9.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY ps2_mouse9 IS -- 顶层设计
PORT ( CLK
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vhd ps2_mouse9.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY ps2_mouse9 IS -- 顶层设计
PORT ( CLK
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vhd elec_lock.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
LIBRARY altera;
USE altera.maxplus2.ALL;
--*************************************
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vhd dispselector_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY dispselector IS
PORT
(CLK: IN STD_LOGIC;
NUM1: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
NUM2: IN STD_LOGIC_VECTO
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vhd dispselector_2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY dispselector IS
PORT
(CLK: IN STD_LOGIC;
NUM1: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
NUM2: IN STD_LOGIC_VECTO
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txt readme.txt
COMM32.PAS
==========
Version 1.00
Comm32.pas is a simple Communications VC for Borland Delphi 2.0 which
demonstrates the Win32 Communications functions and the new Delphi
'TThread' class. I