dds_vhdl.vhd

函数发生器代码

--主程序
--程序名
library ieee;
use ieee.std_logic_1164.all;
entity frqload is 
  port(num:in std_logic_vector(3 downto 0);
    q:out integer range 0 to 312);
end frqload;
architecture a of frqload is   
begin  
 process(num)    
  begin 
case num is
when "0001"=>q<=312;
when "0010"=>q<=155;
when "0011"=>q<=104;
when "0100"=>q<=78;
when "0101"=>q<=63;
when "0110"=>q<=52;
when "0111"=>q<=45;
when "1000"=>q<=39;
when "1001"=>q<=35;
when "1010"=>q<=31;
 when others=>null;
        end case;
    end process;      
end a;
--分频模块
--程序名frq_div.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity frq_div is  
   Port (a:in integer range 0 to 312;
           clk: in std_logic;
           q: out std_logic);
end frq_div;
architecture a of frq_div is 
begin
 process(clk)
variable b,d:std_logic;  
variable num:integer range 0 to 312;
 begin
  if clk'event and clk='1' then
if b='0'then
num:=a-1;
b:='1';
else
if num=1 then
b:='0';
d:=not d;
else 
  num:=num-1;
end if;
end if;
end if;
q<=not d;
    end process;
end a;
--三角波信号发生模块
--程序名:delta_gen.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delta_gen is
    port(clk,reset:in std_logic;
   q:out std_logic_vector(7 downto 0));
end delta_gen;
architecture a of delta_gen is
begin
process(clk,reset)
variable num:std_logic_vector(7 downto 0);
variable ff:std_logic;
begin
 if reset='0'then
   num:="00000000";
elsif clk'event and clk='1'then 
 if  ff='0'then 
  if num="11111000"then
   num:="11111111";
ff:='1';
else
num:=num+8;
end if;
else
 if num="00000111"then
  num :="00000000";
   ff:='0';
   else
    num:=num-8;
   end if;
 end if;
end if;
q<=num;
end process; 
end a;
--方波信号发生模块
--程序名：stuare-gen.vhd 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY square_gen IS
        PORT
    (
        clk, clr : IN STD_LOGIC;
               q : OUT integer range 0 to 255
    );
END square_gen;
ARCHITECTURE a OF square_gen IS
    SIGNAL ff : bit;
BEGIN
process(clk,clr)
variable num:integer range 0 to 512;
begin
    if clr='0'then
    ff<='0';
ELSIF clk'event and clk='1' then

    if num<512 then 
    num:=num+1;
ELSE
    num:=0;
    ff<= not ff;
END IF;
END IF;
END process;
process_label:
PROCESS (clk,ff)
    
BEGIN
    IF clk'event and clk='1' then 
      if ff='1' then
    q<=255;
ELSE
    q<=0;
    
END IF;
END IF;
END PROCESS;
end a;
--正弦波信号发生模块
--程序名：sin_gen.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY sin_gen is
        PORT
    (
        clk, clr : IN   STD_LOGIC;
        d : OUT integer range 0 to 255
    );
END sin_gen;
ARCHITECTURE a OF sin_gen IS
    
BEGIN
    
PROCESS (clk,clr)
    VARIABLE num:integer range 0 to 63;
    
BEGIN
    IF clr='0' then
    d<=0;
ELSIF clk'event and clk='1' then

    if num=63   THEN
    num:=0;
ELSE
    num:=num+1;
END IF;
CASE num iS
WHEN 00=>d<=255;WHEN 01=>d<=254; WHEN 02=>d<=252;

WHEN 03=>d<=249;WHEN 04=>d<=245; WHEN 05=>d<=239;
WHEN 06=>d<=233;WHEN 07=>d<=225; WHEN 08=>d<=217;
WHEN 09=>d<=207;WHEN 10=>d<=197; WHEN 11=>d<=186;
WHEN 12=>d<=174;WHEN 13=>d<=162; WHEN 14=>d<=150;
WHEN 15=>d<=137;WHEN 16=>d<=124; WHEN 17=>d<=112;
WHEN 18=>d<=99; WHEN 19=>d<=87;   WHEN 20=>d<=75;
WHEN 21=>d<=64; WHEN 22=>d<=53;  WHEN 23=>d<=43;
WHEN 24=>d<=34; WHEN 25=>d<=26;  WHEN 26=>d<=19;
WHEN 27=>d<=13; WHEN 28=>d<=8;   WHEN 29=>d<=4;
WHEN 30=>d<=1;  WHEN 31=>d<=0;   WHEN 32=>d<=0;
WHEN 33=>d<=1;  WHEN 34=>d<=4;   WHEN 35=>d<=8;
WHEN 36=>d<=13; WHEN 37=>d<=19;  WHEN 38=>d<=26;

WHEN 39=>d<=34; WHEN 40=>d<=43;  WHEN 41=>d<=53;
WHEN 42=>d<=64; WHEN 43=>d<=75;  WHEN 44=>d<=87;
WHEN 45=>d<=99; WHEN 46=>d<=112; WHEN 47=>d<=124;
WHEN 48=>d<=137;WHEN 49=>d<=150; WHEN 50=>d<=162;
WHEN 51=>d<=174;WHEN 52=>d<=186; WHEN 53=>d<=197;
WHEN 54=>d<=207;WHEN 55=>d<=217; WHEN 56=>d<=225;
WHEN 57=>d<=233;WHEN 58=>d<=239; WHEN 59=>d<=245;
WHEN 60=>d<=249;WHEN 61=>d<=252; WHEN 62=>d<=254;
WHEN 63=>d<=255;            
when others =>null; 
END CASE;
end if ;
end process;
 
END a;
--波形输出选择模块
--程序名:makgrp.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY mkgrp IS
        PORT
    (
        dlt, sqr,sin: IN std_logic;
        dltd,sqrd,sind: in std_logic_vector(7 downto 0);
        q: out std_logic_vector(7 downto 0));
END mkgrp;
ARCHITECTURE a OF mkgrp IS
begin 
process(dlt,dltd,sqr,sqrd,sin,sind)
variable tmp:std_logic_vector(2 downto 0);
variable a,b:std_logic_vector(9 downto 0);
variable c,d,e:std_logic_vector(9 downto 0);
begin
tmp:=dlt&sqr&sin;
case tmp is
WHEN "100"=>q<=dltd;
WHEN "010"=>q<=sqrd;
WHEN "001"=>q<=sind;
when "011"=>a:="00"&sqrd+sind;q<=a(8 downto 1);
when "101"=>a:="00"&dltd+sind;q<=a(8 downto 1);
when "110"=>a:="00"&dltd+sqrd;q<=a(8 downto 1);
when "111"=>a:="00"&dltd+sqrd;
b:=a+sind;
c:="00"&b(9 downto 2);
d:="00"&a(9 downto 2);
e:="00"&a(9 downto 2);
a:=c+d;
b:=a+e;
q<=b(7 downto 0);
when others =>null;
end case; 
end process;
end a;
LIBRARY IEEE;--顶层设计
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dds_vhdl IS
    PORT
    (
                    -- K :IN std_logic_vector(3 downto 0);
              inclk,VCC : IN    STD_LOGIC;
            F_LOAD : IN std_logic_vector(3 downto 0);
        dlt0, sqr0,sin0: IN std_logic;
                output :out std_logic_vector(7 downto 0)
    );
END dds_vhdl;
ARCHITECTURE struc OF dds_vhdl IS
    COMPONENT frqload
        PORT( num:in std_logic_vector(3 downto 0);
              
               q:out std_logic_vector(8 downto 0) ); --out integer range 0 to 312
           
    END COMPONENT;
    COMPONENT frq_div
        PORT(   a:in STD_LOGIC_VECTOR(8 DOWNTO 0);
              clk: in std_logic;
                q: out std_logic
            );
    END COMPONENT;
    COMPONENT delta_gen
        PORT(  clk,reset:in std_logic;
                       q:out std_logic_vector(7 downto 0)
            );
    END COMPONENT;
    COMPONENT square_gen
        PORT( clk, clr : IN STD_LOGIC;
                     q : out std_logic_vector(7 downto 0));--OUT integer range 0 to 255
            
    END COMPONENT;
    COMPONENT sin_gen
        PORT( clk, clr : IN STD_LOGIC;
                     d : out std_logic_vector(7 downto 0));--OUT integer range 0 to 255
         
    END COMPONENT;
    COMPONENT mkgrp
        PORT(  dlt, sqr,sin: in std_logic;
             dltd,sqrd,sind: in std_logic_vector(7 downto 0);
                          q: out std_logic_vector(7 downto 0));
    END COMPONENT;
      --SIGNAL F_LOAD : std_logic_vector(3 downto 0);
      SIGNAL F_DIV  : std_logic_vector(8 downto 0); --integer range 0 to 312;
      SIGNAL DELx    : std_logic_vector(7 downto 0);
      SIGNAL SQUx    : std_logic_vector(7 downto 0);
      SIGNAL SINx    : std_logic_vector(7 downto 0);
      SIGNAL Q_CLK  : std_logic;
BEGIN
--F_LOAD(3 downto 0)=>K;
U1 : frqload PORT MAP (num=>F_LOAD,Q=>F_DIV);
U2 : frq_div PORT MAP (A=>F_DIV,CLK=>inclk,Q=>Q_CLK);
U3 : delta_gen PORT MAP (CLK=>Q_CLK,RESET=>VCC,Q=>DELx);
U4 : square_gen PORT MAP (CLK=>Q_CLK,CLR=>VCC,Q=>SQUx);
U5 : sin_gen PORT MAP (CLK=>Q_CLK,CLR=>VCC,d=>SINx);
U6 : mkgrp PORT MAP (DLT=>dlt0,SQR=>sqr0,SIN=>sin0,DLTD=>DELx,SQRD=>SQUx,SIND=>SINx,Q=>output);
END struc;