dispselector_2.vhd

来自「以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计」· VHDL 代码 · 共 66 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY dispselector IS
	PORT
	(CLK: IN	STD_LOGIC;
	NUM1: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
	NUM2: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
	NUM3: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
	NUM4: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
	NUM5: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
	NUM6: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
	DIGSGN:out std_logic_vector(0 to 7);
	CATSEL:out std_logic_vector(0 to 5)
	);
END dispselector;

ARCHITECTURE arch OF dispselector IS
	SIGNAL DGT : STD_LOGIC_VECTOR(3 DOWNTO 0);--要显示的数字
	SIGNAL POS : integer range 0 to 5;--数字出现的位置

BEGIN

	count6:PROCESS(CLK)
	BEGIN
		if Rising_edge(CLK) then
			if POS>=5 then
				POS<=0;
			else
				POS<=POS+1;
			end if;
		end if;
	END PROCESS count6;

	WITH POS SELECT--阴极控制
		CATSEL<="011111" WHEN 0,
				"101111" WHEN 1,
				"110111" WHEN 2,
				"111011" WHEN 3,
				"111101" WHEN 4,
				"111110" WHEN 5;

	WITH POS SELECT--选择要显示的数位
		DGT<=NUM1 WHEN 0,
			NUM2 WHEN 1,
			NUM3 WHEN 2,
			NUM4 WHEN 3,
			NUM5 WHEN 4,
			NUM6 WHEN 5;

	with DGT select--七段显示信号
		DIGSGN<="11111100" when "0000",
				"01100000" when "0001",
				"11011010" when "0010",
				"11110010" when "0011",
				"01100110" when "0100",
				"10110110" when "0101",
				"10111110" when "0110",
				"11100000" when "0111",
				"11111110" when "1000",
				"11110110" when "1001",
				"00000000" when others;

END arch;