代码搜索：vhdl

找到约 10,000 项符合「vhdl」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/2252/14766

vhd vhdl.vhd

-- generated by newgenasym Wed Oct 29 14:16:34 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity ind is port ( A: INOUT STD_LOGIC; B: INOUT
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www.eeworm.com/read/2252/14789

vhd vhdl.vhd

-- generated by newgenasym Wed Oct 29 14:15:22 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity cappol is port ( N: INOUT STD_LOGIC; P: INOU
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www.eeworm.com/read/2252/14814

vhd vhdl.vhd

-- generated by newgenasym Wed Oct 29 14:14:55 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity cap is port ( A: INOUT STD_LOGIC; B: INOUT
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www.eeworm.com/read/2252/14833

vhd vhdl.vhd

-- generated by newgenasym Thu Oct 30 21:46:29 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity ltc3713 is port ( BG: INOUT STD_LOGIC; BOOST: INO
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www.eeworm.com/read/2252/14850

vhd vhdl.vhd

-- generated by newgenasym Thu Oct 23 15:07:18 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity tle2037a is port ( M: IN STD_LOGIC; N1: OU
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www.eeworm.com/read/2252/14867

vhd vhdl.vhd

-- generated by newgenasym Fri Oct 31 19:08:47 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity \74lvth240\ is port ( A1_1: IN STD_LOGIC; A1_2:
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www.eeworm.com/read/2252/14884

vhd vhdl.vhd

-- generated by newgenasym Wed Oct 22 14:13:23 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity tlc5602 is port ( AGND: IN STD_LOGIC; AOUT: OUT
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www.eeworm.com/read/2252/14901

vhd vhdl.vhd

-- generated by newgenasym Tue Oct 21 18:57:15 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity nvregg79x is port ( GND: IN STD_LOGIC; \in\: I
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www.eeworm.com/read/2252/14918

vhd vhdl.vhd

-- generated by newgenasym Wed Oct 22 12:30:42 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity tl081c is port ( M: IN STD_LOGIC; N1: IN
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www.eeworm.com/read/2252/14935

vhd vhdl.vhd

-- generated by newgenasym Fri Oct 31 17:18:34 2008 library ieee; use ieee.std_logic_1164.all; use work.all; entity \74lvth373\ is port ( D1: IN STD_LOGIC; D2:
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