代码搜索：vhdl
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www.eeworm.com/read/400963/11566537
doc vhdl.doc
www.eeworm.com/read/400878/11567411
doc vhdl.doc
www.eeworm.com/read/400073/11583749
txt vhdl.txt
library ieee;
use ieee.std_logic_1164.all;
entity veryhardd is
port(up1,up,2,clk,down2,down3,k1,k2,k3:in std_logic;
site:out std_logic_vector(3 downto 1);
a1,a2,a3:out std_logic;
www.eeworm.com/read/158465/11612685
txt vhdl.txt
5-1加法器(减法器电路设计
5-1-1全加器电路
--fadd.vhd fadd.vhd one bit full adder
library ieee ;
use ieee.std_logic_1164.all;
entity fadd is
port(
a: in std_logic;--被加数
b: in std_logic;---加数
ci : in std
www.eeworm.com/read/347114/11695008
psm _vhdl.psm
www.eeworm.com/read/347114/11695034
psm _vhdl.psm
www.eeworm.com/read/347114/11695173
psm _vhdl.psm
www.eeworm.com/read/347114/11695221
psm _vhdl.psm
www.eeworm.com/read/347114/11695302
psm _vhdl.psm
www.eeworm.com/read/347114/11695516