vhdl.txt

加法器 乘法器电路 除法器电路设计 键盘扫描电路设计 显示电路

5-1加法器(减法器电路设计
5-1-1全加器电路
--fadd.vhd fadd.vhd one bit full adder
library ieee ;
use ieee.std_logic_1164.all;
entity fadd is
port(
  a: in std_logic;--被加数
  b: in std_logic;---加数
  ci : in std_logic;--进位输入
  co: out std_logic; --进位输出
  sum : out std_logic);--和
end fadd;
architecture behavior of fadd is 
begin 
  co<=(a and b) or (b and ci) or (a and ci);
  sum<=a xor b xor ci;
end behavior;

5-1-2四位连波进位加法器
--fadd4.vhd 4-bit ripple-carry adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity fadd4 is
port(
  	a	: in std_logic_vector(3 downto 0);--被加数
	b 	: in std_logic_vector(3 downto 0);--加数
  	ci 	: in std_logic;--进位输入
  	co 	: out std_logic;--进位输出
  	sum : out std_logic_vector(3 downto 0));--和
end fadd4;
architecture behavior of fadd4 is 
  signal ci_ns : std_logic_vector(2 downto 0);--ci与co的联机
begin 
  u0: fadd  port map (a(0),b(0),ci,ci_ns(0),sum(0));
  u1: fadd  port map (a(1),b(1),ci_ns(0),ci_ns(1),sum(1));
  u2: fadd  port map (a(2),b(2),ci_ns(1),ci_ns(2),sum(2));
  u3: fadd  port map (a(3),b(3),ci_ns(2),co,sum(3));
end behavior;

5-1-3二进制十进码(bcd)加法器电路
--bcdadd.vhd 1 digit bcd adder
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcdadd is
port(
  	a	: in std_logic_vector(3 downto 0);--被加数
	b 	: in std_logic_vector(3 downto 0);--加数
  	ci 	: in std_logic;--进位输入
  	co 	: out std_logic;--进位输出
  	sum : out std_logic_vector(3 downto 0));--和
end bcdadd;
architecture behavior of bcdadd is 
  signal s : std_logic_vector(3 downto 0); --第一个fadd4的和
  signal c4 : std_logic;--第一个fadd4进位输出
  signal a2 : std_logic_vector(3 downto 0);
  signal y : std_logic;--加6侦测内部联机
  signal zero : std_logic;--第二个fadd4的进位保持'0'
  signal nouse : std_logic;--没有使用到的浮接线
begin 
  u0: fadd4 port map (a,b,ci,c4,s);--第1个fadd4
  y<=c4 or (s(3) and s(2)) or (s(3) and s(1));--侦测加6
  a2<='0' & y & y & '0';
  co<=y;--bcd进位输出
  zero<='0'; --第二个fadd4的进位保持'0'
  u1: fadd4 port map (a2,s,zero,nouse,sum);--第2个fadd4
end behavior;

5-1-4 bcd码取九补码电路
--com9s.vhd	9's generator
library ieee ;
use ieee.std_logic_1164.all;
entity com9s is
port(
  a : in std_logic_vector(3 downto 0);--输入
  sel : in std_logic;--取补致能，1=>取补，0=>不变
  z : out std_logic_vector(3 downto 0));--取9补输出
end com9s;
architecture behavior of com9s is 
begin 
  process (sel,a)
  begin
    if sel='1' then
      z(3)<=(not a(3)) and (not a(2)) and (not a(1));                  
      z(2)<=a(2) xor a(1);
      z(1)<=a(1);
      z(0)<=not a(0);
    else   
      z<=a;
    end if;
  end process;
end behavior;

5-1-5 bcd加／减法器电路
--bcd.vhd 1 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd is
port(
  a : in std_logic_vector(3 downto 0);--被加／减数
  b : in std_logic_vector(3 downto 0);--加／减数
  ci : in std_logic;--进位输入，减法模式时为'0'
  sel : in std_logic;--加／减法模式选择，0=>加法，1=>减法
  co : out std_logic;--进位输出
  sum : out std_logic_vector(3 downto 0));--和
end bcd;
architecture behavior of bcd is 
  signal b2 : std_logic_vector(3 downto 0);--加／减取9补结果
begin
  u0: com9s port map (b,sel,b2);--取9补码电路
  u1: bcdadd port map (a,b2,ci,co,sum);--bcd加法器
end behavior;

5-1-6 三个字符的bcd加／减法器
--bcd3.vhd	3 digits bcd adder/subtractor
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity bcd3 is
port(
  a	  : in std_logic_vector(11 downto 0);--被加／减数
  b	  : in std_logic_vector(11 downto 0);--加／减数
  ci  :	in std_logic;--进位输入
  sel : in std_logic;--加／减法模式选择，0=>加法，1=>减法
  co  : out std_logic;--进位输出
  sum : out std_logic_vector(11 downto 0));--和
end bcd3;
architecture behavior of bcd3 is 
  signal cc : std_logic_vector(1 downto 0);--bcd.co ->bcd.ci interconnetcion
begin
  bcd1: bcd port map (a(3 downto 0), b(3 downto 0), ci, sel, cc(0), sum(3 downto 0)) ;
  bcd2: bcd port map (a(7 downto 4), b(7 downto 4), cc(0), sel, cc(1), sum(7 downto 4)) ;
  bcd3: bcd port map (a(11 downto 8), b(11 downto 8), cc(1), sel, co, sum(11 downto 8)) ;
end behavior;

5-1-7负数取补修正电路
--negative.vhd correct negative number circuit
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;
entity negative is
port(
  a : in std_logic_vector(11 downto 0);--输入
  sel : in std_logic;--取补致能，1=>取补，0=>不变
  z : out std_logic_vector(11 downto 0));--取9补输出
end negative;
architecture behavior of negative is 
	signal a2 : std_logic_vector(3 downto 0) ;--取补输出
	signal zero : std_logic_vector(3 downto 0) ;--bcdadd加零
	signal unuse : std_logic ;--未输出co接脚
begin 
	zero <= "0000" ;
	com1: com9s port map (a(3 downto 0), sel, a2);--取9补码电路
	bcd1: bcdadd port map (zero, a2, sel, unuse, z(3 downto 0));--bcd加法器
	com2: com9s port map (a(7 downto 4), sel, z(7 downto 4));--取9补码电路
	com3: com9s port map (a(11 downto 8), sel, z(11 downto 8));--取9补码电路
end behavior;

5-1-8缓存器电路
--regne.vhd n-bit register with enable
library ieee ;
use ieee.std_logic_1164.all ;

entity regne is
generic ( n : integer := 12 ) ;
port (
  r : in 	std_logic_vector(n-1 downto 0) ;--register input
  e : in 	std_logic ;--enable?1->enable 0->disable
  clock : in 	std_logic ;--clock signal
  q : out std_logic_vector(n-1 downto 0) ) ;--register output
end regne ;
architecture behavior of regne is
begin
  process ( clock )
  begin
    if clock'event and clock = '1' then--clock positive edge trigger
      if e = '1' then
        q <= r ;--data store into register
      end if ;
    end if ;
  end process ;
end behavior ;


5-1-9倒数计数器电路
--downcnt.vhd n modules downcounter
library ieee ;
use ieee.std_logic_1164.all ;
entity downcnt is
generic ( modulus : integer := 8 ) ;
port (
	clock : in std_logic ;
	e : in std_logic ;--enable 1->enable 0->disable
	l : in std_logic ;--load 1->load
	q : out	integer range 0 to modulus-1 ) ;
end downcnt ;
architecture behavior of downcnt is
	signal count : integer range 0 to modulus-1 ;
begin
  process
  begin
    wait until (clock'event and clock = '1') ;--clock positive edge trigger
	  if e = '1' then
		if l = '1' then
          count <= modulus-1 ;--loading
		else
		  count <= count-1 ;--counting
		end if ;
	end if ;
  end process;
	q <= count ;--output internal signal
end behavior ;

5-1-10 bcd加／减法器电路
--bcd_add_sub.vhd 3 digits bcd adder/subtractor with start and done
library ieee ;
use ieee.std_logic_1164.all;
use work.components.all;

entity bcd_add_sub is
port(
  clock : in std_logic ;--频率讯号
  s 	: in std_logic ;--operate start enable
  ea 	: in std_logic ;--load a
  eb 	: in std_logic ;--load b
  dataa : in std_logic_vector(11 downto 0) ;--被加／减数
  datab : in std_logic_vector(11 downto 0) ;--加／减数
  sel	: in std_logic ;--加／减模式选择，0=>加,1=>减
  sum 	: out std_logic_vector(15 downto 0) ;--和
  done 	: out std_logic) ;--operate done
end bcd_add_sub;
architecture behavior of bcd_add_sub is 
  type state_type is ( s1, s2 ) ;--state definition of fsm
  signal y		: state_type ;--state delcare of fsm
  signal ec 	: std_logic ;--downcounter enable
  signal lc 	: std_logic ;--downcounter load
  signal z		: std_logic ;--downcounter zero detect
  signal a		: std_logic_vector(11 downto 0) ;--被加／减数register
  signal b		: std_logic_vector(11 downto 0) ;--加／减数registr
  signal count	: integer range 0 to 7 ;--counter
  signal sumc	: std_logic_vector(11 downto 0) ;--bcd.sum -> negative.a interconnection
  signal co 	: std_logic ;--bcd3.co
  signal negative_com 	: std_logic ;--complement enable of negative sum
begin
  fsm_transition: process ( clock )
  begin
	if clock'event and clock = '1' then
		case y is
			when s1 =>
				if z = '0' then y <= s1 ; else y <= s2 ; end if ;
			when s2 =>
				if s = '1' then y <= s2 ; else y <= s1 ; end if ;
		end case ;
	end if ;
  end process ;	
  fsm_output: process (y)
  begin
	case y is
		when s1 =>
			done <= '0' ;
		when s2 =>
			done <= '1' ;
	end case;
  end process;
  --datata register
  rega: regne generic map ( n => 12 )
	port map ( dataa, ea, clock, a ) ;
  --datatb register
  regb: regne generic map ( n => 12 )
	port map ( datab, eb, clock, b ) ;
  --downcounter
  ec <= '1' ; lc <= not s ;
  counter: downcnt generic map ( modulus => 8 ) 
	port map ( clock, ec, lc, count ) ;
  z <= '1' when count = 0 else '0' ;--detect done
  --3 word bcd add/sub circuit
  bcd: bcd3 port map(a, b, sel, sel, co, sumc) ;
  --bcd.sumc 9's only if sel='1' for selecting sub mode and co='0' represent negative sum
  negative_com <= sel and (not co) ;
  --detect minus display and encode
  sum(15 downto 13) <= "000" when negative_com ='0' else "111" ;
  sum(12) <= ((not sel) and co) ;
  --10's negative sum correction circuit
  complement: negative port map(sumc, negative_com, sum(11 downto 0)) ;

end behavior;

5-2乘法器电路
5-2-1左移位缓存器电路
--shiftlne.vhd n-bitright-to-left shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftlne is
generic ( n : integer := 7 ) ;
port(	
  r	: in std_logic_vector(n-1 downto 0) ;--register input
  l	: in std_logic ;--load
  e	: in std_logic ;--enable
  w	: in std_logic ;--series input
  clock	: in std_logic ;--clock
  q	: buffer std_logic_vector(n-1 downto 0) ) ;--register output
end shiftlne ;
architecture behavior of shiftlne is
begin
  process
  begin
	wait until clock'event and clock = '1' ;
	if e = '1' then
      if l = '1' then
		q <= r ;--parallel load
	  else
	    q(0) <= w ;--series input to lowest bit
	    genbits: for i in 1 to n-1 loop
		  q(i) <= q(i-1) ;--shift low bit to high bit
	    end loop ;
	  end if ;
	end if ;
  end process ;
end behavior ;

5-2-2右移位缓存器电路
--shiftrne.vhd n-bit left-to-right shift register
--with parallel load and enable
library ieee ;
use ieee.std_logic_1164.all ;
entity shiftrne is
generic ( n : integer := 7 ) ;
port ( 	
  r : in std_logic_vector(n-1 downto 0) ;--register input
  l : in std_logic ;--load
  e : in std_logic ;--enable
  w : in std_logic ;--series input
  clock	: in std_logic ;--clock
  q	: buffer std_logic_vector(n-1 downto 0) ) ;--register output
end shiftrne ;
architecture behavior of shiftrne is	
begin
  process
  begin
    wait until clock'event and clock = '1' ;
	  if e = '1' then
		if l = '1' then
		  q <= r ;--parallel load
		else
		  genbits: for i in 0 to n-2 loop
		    q(i) <= q(i+1) ;--shift high bit to low bit 
	      end loop ;
		  q(n-1) <= w ;--series input to highest bit
		end if ;
	  end if ;
  end process ;
end behavior ;

5-2-3 2对１多任务器 
--mux2to1.vhd n-bit 2-to-1 multiplexer
library ieee ;
use ieee.std_logic_1164.all ;
entity mux2to1 is
generic ( n : integer := 14 ) ;
port (	
  w0 : in 	std_logic_vector(n-1 downto 0) ;--input first term
  w1 : in 	std_logic_vector(n-1 downto 0) ;--input second term
  s	: in 	std_logic ;--select line
  f	: out 	std_logic_vector(n-1 downto 0) ) ;--output seleted term
end mux2to1 ;
architecture behavior of mux2to1 is
begin
  with s select
  f <= w0 when '0',
       w1 when others ;
end behavior ;
5-2-4 乘法器电路
--multiplier.vhd n-bit multiplier
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity multiplier is
generic ( n : integer := 7; nn : integer := 14 ) ;
port (	
  clock	: in std_logic ;--clock
  la : in std_logic ;--load of multiplicand
  lb : in std_logic ;--load of multiplier
  s	: in std_logic ;--start
  dataa	: in std_logic_vector(n-1 downto 0) ;--multiplicand
  datab	: in std_logic_vector(n-1 downto 0) ;--multiplier
  p	: buffer std_logic_vector(nn-1 downto 0) ;--porduct
  done : out std_logic ) ;
end multiplier ;
architecture behavior of multiplier is
  type state_type is ( s1, s2, s3 ) ;--state define
  signal y : state_type ;--state declaration
  signal psel: std_logic ;--select line of multiplexer
  signal z : std_logic ;--detecter of zero 
  signal ea : std_logic ;--enable of shift-left register(multiplicand)
  signal eb : std_logic ;--enable of shift-right register(multiplier)
  signal ep : std_logic ;--enable of product register
  signal zero : std_logic ;--series input of shift
  signal b : std_logic_vector(n-1 downto 0) ;--output of shift-right register
  signal n_zeros : std_logic_vector(n-1 downto 0) ;--n-bit zero load into register with multiplicand
  signal a : std_logic_vector(nn-1 downto 0) ;--output of shift-left register
  signal ain : std_logic_vector(nn-1 downto 0) ;--input of shift-left regster
  signal datap : std_logic_vector(nn-1 downto 0) ;--output of multiplexer 
  signal sum : std_logic_vector(nn-1 downto 0) ;--sum of product and multiplicand
  signal nn_zeros : std_logic_vector(nn-1 downto 0) ;--2*n-bit zero input to multiplicand
  signal q : integer range 0 to n;--count of downcounter
  signal ec : std_logic;--enable of downcounter
  signal lc : std_logic;--load of downcounter
begin
  fsm_transitions: process ( clock )
  begin
	if (clock'event and clock = '1') then
      case y is
	    when s1 =>
		  if s = '0' then	y <= s1 ; else y <= s2 ; end if ;
		when s2 =>
		  if z = '0' then y <= s2 ; else y <= s3 ; end if ;
		when s3 =>
		  if s = '1' then y <= s3 ; else y <= s1 ; end if ;
		end case ;
	end if ;
  end process ;

  fsm_outputs: process ( y, s, la, lb, b(0) )
  begin
    ep <= '0' ; ea <= '0' ; eb <= '0' ; done <= '0' ; psel <= '0';
    case y is
	  when s1 =>
		ep <= '1' ;
		if s = '0' and la = '1' then ea <= '1' ; 
		else ea <= '0' ; end if ;
		if s = '0' and lb = '1' then eb <= '1' ; 
		else eb <= '0' ; end if ;
	  when s2 =>