vhdl.txt

电梯控制器的模块电路

library ieee;
use ieee.std_logic_1164.all;
entity veryhardd is 
  port(up1,up,2,clk,down2,down3,k1,k2,k3:in std_logic;
       site:out std_logic_vector(3 downto 1);
       a1,a2,a3:out std_logic;
       mode,door:out std_logic);
end veryhardd;
architecture veryhard_arc of veryhardd is
type state_type is (c1,c2,c3,kai);
begin
  process(clk)
  variable up1,down1,ting1,ceng1:std_logic_vector(3 downto 1);
  variable mo,x,y,z:std_logic;
  variable cnt1,cnt2:integer;
  variable state:state_type;
  begin
   if clk'event and clk='1'then
    if up1='0'then
       up1(1):='1';
     end if;
   if up2='0'then
      up1(2):='1';
     end if;
   if down3='0'then
       down(3):='1';
     end if;
  if down2='0'then
       down(2):='1';
     end if;
  if k1='0'then
     ting1(1):='1';
     end if;
  if k2='0'then
     ting1(2):='1';
     end if;
  if k3='0'then
     ting1(3):='1';
     end if;
  if cnt1<1000 then
     cnt1:=cnt1+1;
  else 
    case state is
       when c1=>ceng1:="001";
                 mo:='0';
       if up1/="000" or down1/="000" or ting1/="000" then
          z:='1';
       end if;
       if z='0' then
       door<='1';
      else 
      door<='0';
     if ting1(1)='1' or up1(1)='1' then
          state:=kai;
          ting1(1):='0';
          up1(1):='0';
 elsif up1(2)='1' or ting1(2)='1' then
        state:=c2;
 elsif down1(3)='1' or ting1(3)='1' then
       state:=c2;
       x:='1';
 elsif down1(2)='1' then
    state:=c2;
   mo:='1';
  end if;
  end if;
when c2=>ceng1:="010";
     if mo='0' then
        if ting1(2)='1' or up1(2)='1' then 
     state:=kai;
     ting1(2):='0';
     up1(2):='0';
  elsif down1(3)='1' or ting1(3)='1' or x='1' then
  state:=c3;
  x:='0';
  elsif down1(2)='1' or up1(1)='1' or ting1(1)='1' then
     mo:='1';
   end if;
else
      if ting1(2)='1' or down1(2)='1' then
        state:=kai;
        ting1(2):='0';
        down1(2):='0';
      elsif up1(1)='1' or ting1(1)='1' or y='1' then
        state:=c1;
        y:='0';
      elsif up1(2)='1' or down1(3)='1' or ting1(3)='1' then
         mo:='0';
      end if;
      end if;
when c3=>mo:='1';
            ceng1:="100";
            if ting1(3)='1' or down1(3)='1' then
                         state :=kai;
                         ting1(3):='0';
                         down1(3):='0';
             elsif down1(2)='1' or ting1(2)='1' then
                         state:=c2;
             elsif up1(1)='1' or ting1(1)='1' then 
                         state:=c2;
                          y:='1';
            elsif up1(2)='1' then
                         state:=c2;
                        mo:='0';
            end if;
when kai=>door<='1';
                if cnt2<3 then
                    cnt2:=cnt2+1;
                else 
                    door<='0';
                    cnt2:='0';
             if ceng1="001" then
                    state:=c1;
             elsif ceng1="010" then
                    state:=c2;
             else
                    state:=c3;
                end if;
                 end if;
           end case;
           cnt1:=0;
       end if;
end if;
site<=ceng1;
a1<=ting1(1);
a2<=ting1(2);
a3<=ting1(3);
mode<=mo;
end process;
end veryhard_arc;



library ieee;
use ieee.std_logic_1164.all;
entity seg is
    port(a:in std_logic_vector(3 downto 1);
             clk:in std_logic;
             q:out std_logic_vector(6 downto 0));
end seg;
architecture seg_arc of seg is
begin
       process(clk)
       begin
               if clk'event and clk='1' then
                       case a is
                        when"001"=>q<="0000110";
                        when"010"=>q<="1011011";
                        when"100"=>q<="1001111";
                               when others=>null;
          end case;
         end if;
       end process;
 end seg_arc;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dian is
      port(clk,mode,in std_logic;
               sel:out std_logic_vector(3 downto 0);
               q:out std_logic_vector(0 to 15));
end dian;
architecture dian_arc of dian is 
begin
         process(clk)
         variable seel:std_logic_vector(3 downto 0);
         begin
            if clk'event and clk='1' then
                seel:=seel+1;
                if mode='0' then
                    case seel is 
                     when "0011"=>q<="0000110000000000";
                     when "0100"=>q<="0001100000000000";
                     when "0101"=>q<="0011000000000000";
                     when "0110"=>q<="0110000000000000";
                     when "0111"=>q<="1111111111111111";
                     when "1000"=>q<="1111111111111111";
                     when "1001"=>q<="0110000000000000";
                     when "1010"=>q<="0011000000000000";
                     when "1011"=>q<="0001100000000000";
                     when "1100"=>q<="0000110000000000";
                     when  others =>q<="0000000000000000";
              end case;
      else
           case seel is 
                    when "0011"=>q<="0000000000110000";
                    when "0100"=>q<="0000000000011000";
                    when "0101"=>q<="0000000000001100";
                    when "0110"=>q<="0000000000000110";
                    when "0111"=>q<="1111111111111111";
                    when "1000"=>q<="1111111111111111";
                    when "1001"=>q<="0000000000000110";
                    when "1010"=>q<="0000000000001100";
                    when "1011"=>q<="0000000000011000";
                    when "1100"=>q<="0000000000110000";
                    when  others =>q<="0000000000000000";
           end case;
     end if;
     end if;
      sel<=seel;
   end process;
  end dian_arc;